Pcie Clock; Pci Express Lane Size Select Jumper J7; Vcu118 Board Fpga U1 To Pcie Edge U2 Connections - Xilinx VCU118 User Manual

X-Ref Target - Figure 3-11
PCIe lane width/size is selected by jumper J7 shown in
selection is 16-lane (J7 pins 7 and 8 jumpered).
X-Ref Target - Figure 3-12
Table 3-21 lists the PCIe U2 edge connector wiring to FPGA U1.
Table 3-21: VCU118 Board FPGA U1 to PCIe Edge U2 Connections
FPGA (U1) Pin
Y7
Y6
AB7
AB6
AD7
AD6
AF7
AF6
AH7
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Figure 3-11: PCIe Clock
Figure 3-12: PCI Express Lane Size Select Jumper J7
FPGA (U1) Pin Schematic Net
Name
MGTYTXP3_227 PCIE_TX0_P
MGTYTXN3_227 PCIE_TX0_N
MGTYTXP2_227 PCIE_TX1_P
MGTYTXN2_227 PCIE_TX1_N
MGTYTXP1_227 PCIE_TX2_P
MGTYTXN1_227 PCIE_TX2_N
MGTYTXP0_227 PCIE_TX3_P
MGTYTXN0_227 PCIE_TX3_N
MGTYTXP3_226 PCIE_TX4_P
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Chapter 3: Board Component Descriptions
Figure 3-12. The default lane size
X17997-100416
Name
Pin Num
A16
A17
A21
A22
A25
A26
A29
A30
A35
X17998-100416
PCIe Edge U2
Pin Name
HSIN(0)
HSIP(0)
HSIN(1)
HSIP(1)
HSIN(2)
HSIP(2)
HSIN(3)
HSIP(3)
HSIP(4)
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