J2 Vita 57.1 Fmc Hpc1 Connections - Xilinx VCU118 User Manual

The HPC1 J2 connections to FPGA U1 are documented in
Table 3-31: J2 VITA 57.1 FMC HPC1 Connections
J2
FMC
Schematic Net Name
HPC1
Pin
C2 NC
C3 NC
C6 NC
C7 NC
C10 FMC_HPC1_LA06_P
C11 FMC_HPC1_LA06_N
C14 FMC_HPC1_LA10_P
C15 FMC_HPC1_LA10_N
C18 FMC_HPC1_LA14_P
C19 FMC_HPC1_LA14_N
C22 FMC_HPC1_LA18_CC_P
C23 FMC_HPC1_LA18_CC_N
C26 FMC_HPC1_LA27_P
C27 FMC_HPC1_LA27_N
C30 FMC_HPC1_IIC_SCL (5)
C31 FMC_HPC1_IIC_SDA (5)
C34 GA0 = 0 = GND
C35 VCC12_SW
C37 VCC12_SW
C39 UTIL_3V3
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
FPGA
I/O
(U1)
Standard
Pin
J2 Sections A/B are no connects (not connected to FPGA U1)
J2 Sections C/D Connections to FPGA U1
NA NA
NA NA
NA NA
NA NA
LVDS BD13
LVDS BE13
LVDS BB13
LVDS BB12
LVDS AW7
LVDS BB16
LVDS AP12
LVDS AR12
LVDS AL14
LVDS AM14
U80.9
U80.8
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Chapter 3: Board Component Descriptions
Table
J2
FMC
Schematic Net Name
HPC1
Pin
D1 VADJ_1V8_PGOOD_LS (1)
D4 NC
D5 NC
D8 FMC_HPC1_LA01_CC_P
D9 FMC_HPC1_LA01_CC_N
D11 FMC_HPC1_LA05_P
D12 FMC_HPC1_LA05_N
D14 FMC_HPC1_LA09_P
D15 FMC_HPC1_LA09_N
D17 FMC_HPC1_LA13_P
D18 FMC_HPC1_LA13_N
D20 FMC_HPC1_LA17_CC_P
D21 FMC_HPC1_LA17_CC_N
D23 FMC_HPC1_LA23_P
D24 FMC_HPC1_LA23_N
D26 FMC_HPC1_LA26_P
D27 FMC_HPC1_LA26_N
D29 FMC_HPC1_TCK_BUF (2)
D30 FMCP_HSPC_TDO_HPC1_TDI (3)
D31 FMC_HPC1_TDO (3)
D32 UTIL_3V3
D33 FMC_HPC1_TMS_BUF (2)
D34 NC
D35 GA1 = 0 = GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
3-31.
I/O FPGA
Standard (U1) Pin
LVCMOS18 AK35
NA NA
NA NA
LVDS AY9
LVDS BA9
LVDS BE14
LVDS BF14
LVDS BA14
LVDS BB14
LVDS AY8
LVDS AY7
LVDS AR14
LVDS AT14
LVDS AN16
LVDS AP16
LVDS AK15
LVDS AL15
U19.16
U132.1,U
26.2,J22.
D31
U132.2,U
13.8
U19.19
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