Vcu118 Fpga U1 Gty Transceiver Bank 121 Connections - Xilinx VCU118 User Manual

Table 3-9: VCU118 FPGA U1 GTY Transceiver Bank 121 Connections
MGT FPGA FPGA (U1) Pin
Bank (U1) Pin Name
AT42 MGTYTXP0_121
AT43 MGTYTXN0_121
AR45 MGTYRXP0_121
AR46 MGTYRXN0_121
AP42 MGTYTXP1_121
AP43 MGTYTXN1_121
AN45 MGTYRXP1_121
AN46 MGTYRXN1_121
AM42 MGTYTXP2_121
AM43 MGTYTXN2_121
AL45 MGTYRXP2_121
GTY
Bank
AL46 MGTYRXN2_121
121
AL40 MGTYTXP3_121
AL41 MGTYTXN3_121
AJ45 MGTYRXP3_121
AJ46 MGTYRXN3_121
AK38 MGTREFCLK0P_121
AK39 MGTREFCLK0N_121
AH38 MGTREFCLK1P_121
AH39 MGTREFCLK1N_121
BF43 MGTRREF_LS
BF42 MGTAVTTRCAL
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Connected
Schematic Net Name
FMCP_HSPC_DP0_C2M_P
FMCP_HSPC_DP0_C2M_N
FMCP_HSPC_DP0_M2C_P
FMCP_HSPC_DP0_M2C_N
FMCP_HSPC_DP1_C2M_P
FMCP_HSPC_DP1_C2M_N
FMCP_HSPC_DP1_M2C_P
FMCP_HSPC_DP1_M2C_N
FMCP_HSPC_DP2_C2M_P
FMCP_HSPC_DP2_C2M_N
FMCP_HSPC_DP2_M2C_P
FMCP_HSPC_DP2_M2C_N
FMCP_HSPC_DP3_C2M_P
FMCP_HSPC_DP3_C2M_N
FMCP_HSPC_DP3_M2C_P
FMCP_HSPC_DP3_M2C_N
FMCP_HSPC_GBT0_0_P
FMCP_HSPC_GBT0_0_N
FMCP_HSPC_GBT1_0_P
FMCP_HSPC_GBT1_0_N
MGTRREF_121
MGTAVTT_FPGA
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Chapter 3: Board Component Descriptions
Connected Pin
Pin Name
C2 DP0_C2M_P
C3 DP0_C2M_N
C6 DP0_M2C_P
C7 DP0_M2C_N
A22 DP1_C2M_P
A23 DP1_C2M_N
A2 DP1_M2C_P
A3 DP1_M2C_N
A26 DP2_C2M_P
A27 DP2_C2M_N
A6 DP2_M2C_P
A7 DP2_M2C_N
A30 DP3_C2M_P
A31 DP3_C2M_N
A10 DP3_M2C_P
A11 DP3_M2C_N
1 Q0
2 NQ0
5 Q0_P
6 Q0_N
R175.1 100Ω 1% P/U to MGTAVTT_FPGA
NA NA
Send Feedback
Connected
Device
FMC+ HSPC J22
U40 ICS85411A
clock buffer
U39 ICS855S006I
clock buffer
NA
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