Vcu118 Fpga U1 Gty Transceiver Bank 226 Connections - Xilinx VCU118 User Manual

Table 3-16: VCU118 FPGA U1 GTY Transceiver Bank 226 Connections
FPGA
MGT
(U1) FPGA (U1) Pin Name
Bank
Pin
AN5 MGTYTXP0_226
AN4 MGTYTXN0_226
AH2 MGTYRXP0_226
AH1 MGTYRXN0_226
AM7 MGTYTXP1_226
AM6 MGTYTXN1_226
AG4 MGTYRXP1_226
AG3 MGTYRXN1_226
AK7 MGTYTXP2_226
AK6 MGTYTXN2_226
GTY
AF2 MGTYRXP2_226
Bank
AF1 MGTYRXN2_226
226
AH7 MGTYTXP3_226
AH6 MGTYTXN3_226
AE4 MGTYRXP3_226
AE3 MGTYRXN3_226
AG9 MGTREFCLK0P_226
AG8 MGTREFCLK0N_226
AE9 MGTREFCLK1P_226
AE8 MGTREFCLK1N_226
BD2 MGTRREF_RS
BD3 MGTAVTTRCAL_RS
Notes:
1. Ensure that the GTY RefClock being sourced into the RefClock SMAs (J30, J31) is AC coupled for proper clocking operation of
GTY transceivers. Use inline SMA DC blocking capacitors if frequency source output is not AC coupled.
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Schematic Net
Connected Pin
Name
PCIE_TX7_P
PCIE_TX7_N
PCIE_RX7_P
PCIE_RX7_N
PCIE_TX6_P
PCIE_TX6_N
PCIE_RX6_P
PCIE_RX6_N
PCIE_TX5_P
PCIE_TX5_N
PCIE_RX5_P
PCIE_RX5_N
PCIE_TX4_P
PCIE_TX4_N
PCIE_RX4_P
PCIE_RX4_N
(1)
MGT226_CLK0_P
(1)
MGT226_CLK0_N
MGTRREF_226
MGTAVTT_FPGA
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Chapter 3: Board Component Descriptions
Connected Pin
Name
A47 HSIP(7)
A48 HSIN(7)
B45 HSOP(7)
B46 HSON(7)
A43 HSIP(6)
A44 HSIN(6)
B41 HSOP(6)
B42 HSON(6)
A39 HSIP(5)
A40 HSIN(5)
B37 HSOP(5)
B38 HSON(5)
A35 HSIP(4)
A36 HSIN(4)
B33 HSOP(4)
B34 HSON(4)
J31 1
J30 1
NC
NC
R1088.1 100Ω 1% P/U to MGTAVTT_FPGA
NA NA
Send Feedback
Connected
Device
PCIe EDGE Conn.
U2
SMA Connectors
J31(P), J30(N)
NA
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