J22 Vita 57.4 Fmcp Hscp Connections - Xilinx VCU118 User Manual

The FMCP J22 connections to FPGA U1 are documented in
Table 3-32: J22 VITA 57.4 FMCP HSCP Connections
J22
FMCP
Schematic Net Name
HSCP
Pin
A2 FMCP_HSPC_DP1_M2C_P
A3 FMCP_HSPC_DP1_M2C_N
A6 FMCP_HSPC_DP2_M2C_P
A7 FMCP_HSPC_DP2_M2C_N
A10 FMCP_HSPC_DP3_M2C_P
A11 FMCP_HSPC_DP3_M2C_N
A14 FMCP_HSPC_DP4_M2C_P
A15 FMCP_HSPC_DP4_M2C_N
A18 FMCP_HSPC_DP5_M2C_P
A19 FMCP_HSPC_DP5_M2C_N
A22 FMCP_HSPC_DP1_C2M_P
A23 FMCP_HSPC_DP1_C2M_N
A26 FMCP_HSPC_DP2_C2M_P
A27 FMCP_HSPC_DP2_C2M_N
A30 FMCP_HSPC_DP3_C2M_P
A31 FMCP_HSPC_DP3_C2M_N
A34 FMCP_HSPC_DP4_C2M_P
A35 FMCP_HSPC_DP4_C2M_N
A38 FMCP_HSPC_DP5_C2M_P
A39 FMCP_HSPC_DP5_C2M_N
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
FPGA
I/O (U1)
Standard Pin
J22 Sections A/B Connections to FPGA U1
AN45
LVDS
LVDS AN46
LVDS AL45
LVDS AL46
LVDS AJ45
LVDS AJ46
LVDS W45
LVDS W46
LVDS U45
LVDS U46
LVDS AP42
LVDS AP43
LVDS AM42
LVDS AM43
LVDS AL40
LVDS AL41
LVDS T42
LVDS T43
LVDS P42
LVDS P43
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Chapter 3: Board Component Descriptions
Table
J22
FMCP
Schematic Net Name
HSCP
Pin
B1 NC
B4 FMCP_HSPC_DP9_M2C_P
B5 FMCP_HSPC_DP9_M2C_N
B8 FMCP_HSPC_DP8_M2C_P
B9 FMCP_HSPC_DP8_M2C_N
B12 FMCP_HSPC_DP7_M2C_P
B13 FMCP_HSPC_DP7_M2C_N
B16 FMCP_HSPC_DP6_M2C_P
B17 FMCP_HSPC_DP6_M2C_N
B20 FMCP_HSPC_GBTCLK1_M2C_P
B21 FMCP_HSPC_GBTCLK1_M2C_N
B24 FMCP_HSPC_DP9_C2M_P
B25 FMCP_HSPC_DP9_C2M_N
B28 FMCP_HSPC_DP8_C2M_P
B29 FMCP_HSPC_DP8_C2M_N
B32 FMCP_HSPC_DP7_C2M_P
B33 FMCP_HSPC_DP7_C2M_N
B36 FMCP_HSPC_DP6_C2M_P
B37 FMCP_HSPC_DP6_C2M_N
B40 NC
3-32.
FPGA
I/O
(U1)
Standard
Pin
NA NA
LVDS AF43
LVDS AF44
LVDS AG45
LVDS AG46
LVDS N45
LVDS N46
LVDS R45
LVDS R46
LVDS U39.2
LVDS U39.1
LVDS AJ40
LVDS AJ41
LVDS AK42
LVDS AK43
LVDS K42
LVDS K43
LVDS M42
LVDS M43
NA NA
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