Vcu118 Gpio Connections To Fpga U1 - Xilinx VCU118 User Manual

Table 3-29 lists the GPIO connections to FPGA U1.
Table 3-29: VCU118 GPIO Connections to FPGA U1
FPGA (U1) Pin
GPIO LEDs (Active-High) GPIO_LED signals are wired to FET LED drivers
BANK 40
BANK 40
BANK 40
BANK 40
BANK 40
BANK 42
BANK 42
BANK 42
Directional pushbuttons (Active-High) are wired in parallel to FPGA BANK 64 and system controller U111
Bank 501
BANK 64
BANK 501
U111
BANK 64
BANK 501
U111
BANK 64
BANK 501
U111
BANK 64
BANK 501
U111
BANK 64
BANK 501
U111
CPU reset pushbutton (active-high)
BANK 73
4-Pole DIP SW (active-high)
BANK 73
BANK 73
BANK 73
BANK 72
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Schematic Net
Name
AT32 GPIO_LED_0
AV34 GPIO_LED_1
AY30 GPIO_LED_2
BB32 GPIO_LED_3
BF32 GPIO_LED_4
AU37 GPIO_LED_5
AV36 GPIO_LED_6
BA37 GPIO_LED_7
BB24
GPIO_SW_N
A13
BE23
GPIO_SW_E
B14
BF22
GPIO_SW_W
D14
BE22
GPIO_SW_S
C14
BD23
GPIO_SW_C
B12
L19 CPU_RESET
B17 GPIO_DIP_SW0
G16 GPIO_DIP_SW1
J16 GPIO_DIP_SW2
D21 GPIO_DIP_SW3
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Chapter 3: Board Component Descriptions
FPGA (U1)
I/O Standard
Direction
Output LVCMOS12
Output LVCMOS12
Output LVCMOS12
Output LVCMOS12
Output LVCMOS12
Output LVCMOS12
Output LVCMOS12
Output LVCMOS12
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS18
Input LVCMOS12
Input LVCMOS12
Input LVCMOS12
Input LVCMOS12
Input LVCMOS12
Device
DS7
DS6
DS8
DS9
DS10
DS12
DS13
DS18
SW10.3
SW9.3
SW6.3
SW17.3
SW7.3
SW5.3
SW12.4
SW12.3
SW12.2
SW12.1
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