Programmable User Clock 1 - Xilinx VCU118 User Manual

On power-up, the U18 SI570 user clock defaults to an output frequency of 156.250 MHz.
The system controller and user applications can change the output frequency within the
range of 10 MHz to 810 MHz. Power cycling the VCU118 evaluation board resets the user
clock to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
• Frequency tolerance: 50 ppm
• 3.3V LVDS differential output
Three additional clocks are sourced from the SI5335A U122 quad clock generator:
• Output CLK1: 125 MHz LVDS signal pair CLK_125MHZ_P and CLK_125MHZ_N,
connected to XCVU9P FPGA U1 bank 64 pins AY24 and AY23, respectively.
• Output CLK2: 90.0 MHz single-ended 1.8V LVCMOS, series resistor coupled
FPGA_EMCCLK, connected to XCVU9P FPGA U1 bank 65 dedicated EMCCLK input pin
AL20.
• Output CLK3: 33.3333 MHz single-ended 1.8V LVCMOS, series resistor coupled
SYSCTLR_CLK, connected to system controller.

Programmable User Clock 1

[Figure 2-1, callout 12]
The VCU118 evaluation board has a SI570 programmable low-jitter 3.3V LVDS differential
oscillator (U32) connected to the CLK0 P/N inputs (pins 6 (P) and 7 (N)) of clock
MUX/quad-buffer SI53340 U104.
The 3.3V SI53340 U104 has four LVDS output clock pairs:
• U104 output Q0 drives clock pair USER_SI570_CLOCK_P/N, connected to XCVU9P FPGA
U1 HP bank 47 GC pins H32 and G32, respectively.
• U104 output Q1 drives clock pair MGT_SI570_CLOCK1_P/N, connected to XCVU9P FPGA
U1 GTY BANK 225 MGTREFCLK1 P/N pins AJ9 and AJ8 (series capacitor coupled),
respectively.
• U104 output Q2 drives clock pair MGT_SI570_CLOCK2_P/N, connected to XCVU9P FPGA
U1 GTY bank 232 MGTREFCLK0 P/N pins R9 and R8 (series capacitor coupled),
respectively.
• U104 output Q3 drives clock pair MGT_SI570_CLOCK3_P/N, connected to XCVU9P FPGA
U1 GTY BANK 233 MGTREFCLK0 P/N pins L9 and L8 (series capacitor coupled),
respectively.
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Chapter 3: Board Component Descriptions
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