Vcu118 Board Constraints File Listing; Appendix B: Master Constraints File Listing; Overview - Xilinx VCU118 User Manual

Master Constraints File Listing

Overview

The master Xilinx design constraints (XDC) file template for the VCU118 board provides for
designs targeting the VCU118 evaluation board. Net names in the constraints listed
correlate with net names on the latest VCU118 evaluation board schematic. Users must
identify the appropriate pins and replace the net names with net names in the user RTL. See
the Vivado Design Suite User Guide: Using Constraints (UG903)
information.
For detailed I/O standards information required for a particular interface, see the constraint
files generated by tools such as the memory interface generator (MIG) and base system
builder (BSB).
The FMC connectors J22 (FMCP) and J2 (FMC HPC1) are connected to 1.8V VADJ banks.
Because different FMC cards implement different circuitry, the FMC bank I/O standards
must be uniquely defined by each customer.
The XDC file can be accessed on the
IMPORTANT:

VCU118 Board Constraints File Listing

# CLOCKS
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
set_property IOSTANDARD
set_property PACKAGE_PIN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
VCU118 Evaluation Kit
G31 [get_ports "SYSCLK1_300_P"];
DIFF_SSTL12 [get_ports "SYSCLK1_300_P"];
F31 [get_ports "SYSCLK1_300_N"];
DIFF_SSTL12 [get_ports "SYSCLK1_300_N"];
AY24 [get_ports "CLK_125MHZ_P"];
LVDS [get_ports "CLK_125MHZ_P"];
AY23 [get_ports "CLK_125MHZ_N"];
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Appendix B
[Ref 11] for more
website.
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