Jumpers; Vcu118 Board Header Jumper Locations - Xilinx VCU118 User Manual

Jumpers

Figure 2-2 shows the VCU118 board jumper header locations. Each numbered component
shown in the figure is keyed to
references the respective schematic page numbers.
X-Ref Target - Figure 2-2
8
Table 2-3: Default Jumper Settings
Jumper Function
J5 Power on reset (POR) override
J7 PCIe lane size select
J8 SYSCLK source select
J9 USER/MGT_SI570 source select
J12 Maxim regulator inhibit
J14 U30 VADJ_1V8 enable
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Table 2-3, which identifies the default jumper settings and
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Figure 2-2: VCU118 Board Header Jumper Locations
Default
2-3 U1 POR_OVERRIDE pin AG12 to GND
7-8 16-lane configuration
Off SI5335A 300 MHz default
Off SI570 U32 156.250 MHz
Off Used when programming PWR. SYS.
Input to U25 AND, VADJ_1V8
Off
enabled
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Chapter 2: Board Setup and Configuration
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Comments
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X18026-100416
Figure 2-2 Schematic
Callout Page
1 3
2 43
3 44
4 45
5 59
6 63
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