Fpga U1 To Cp2105Gm U34 Connections; I2C Bus, Topology, And Switches - Xilinx VCU118 User Manual

Table 3-26 lists the FPGA U1 connections to dual-UART U34.
Table 3-26: FPGA U1 to CP2105GM U34 Connections
FPGA
Function Direction
(U1) Pin
The USB UART signal nets are named from the perspective of the CP2105GM device (U34)
AW25 RX Input
BB21 TX Output
AY25 CTS Input
BB22 RTS Output
For more technical information on the CP2105GM and the VCP drivers, see the Silicon Labs
website [Ref 12].
Xilinx UART IP is expected to be implemented in the FPGA logic using IP. See the AXI UART
Lite LogiCORE IP Product Guide (PG142)

I2C Bus, Topology, and Switches

[Figure 2-1, callouts 22, 23]
The VCU118 evaluation board implements a 2-to-1 I
bank 64 (VCCO VCC1V8_FPGA) and system controller are wired to the same
IIC_MAIN_SDA/SCL I²C bus. The common I²C bus is then routed to a pair of 1-to-8 channel
TI TCA9548 bus switches U28 (address 0x74) and U80 (address 0x75). The bus switches can
operate at speeds up to 400 kHz. The VCU118 evaluation board I²C bus topology overview
is shown in Figure
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Schematic Net
Standard Name
LVCMOS18 USB_UART_TX
LVCMOS18 USB_UART_RX
LVCMOS18 USB_UART_RTS
LVCMOS18 USB_UART_CTS
[Ref 10]
3-18.
www.xilinx.com
Chapter 3: Board Component Descriptions
CP2105GM Device (U34)
Pin Function
21 TXD
20 RXD
19 RTS
18 CTS
for more information.
2
C bus arrangement. The FPGA U1 HP
Send Feedback
Direction
Output
Input
Output
Input
81