Jitter Attenuated Clock - Xilinx VCU118 User Manual

Jitter Attenuated Clock

[Figure 2-1, callout 16]
The VCU118 board includes a Silicon Labs Si5328B jitter attenuator U57 on the back side of
the board. The FPGA U1 QSFP1/QSFP2 control interface bank 64 can output QSFP RX
differential clocks (QSFP1_RECCLK_P, pin AM23 and QSFP1_RECCLK_N, pin AM22, and
QSFP2_RECCLK_P, pin AP23 and QSFP2_RECCLK_N, pin AP22) for jitter attenuation. The jitter
attenuated clock (SI5328_CLOCK1_C_P (U57 output pin 28), SI5328_CLOCK1_C_N (U57
output pin 29)) is routed as a reference clock to FPGA U1 GTY Quad 231 inputs
MGTREFCLK1P (U1 pin U9) and MGTREFCLK1N (U1 pin U8). The jitter attenuated clock
(SI5328_CLOCK2_C_P (U57 output pin 35), SI5328_CLOCK2_C_N (U57 output pin 34)) is
routed as a reference clock to FPGA U1 GTY Quad 232 inputs MGTREFCLK1P (U1 pin N9) and
MGTREFCLK1N (U1 pin N8).
The primary purpose of this clock is to support synchronous protocols, such as common
packet radio interface (CPRI™) or open base station architecture initiative (OBSAI). These
synchronous protocols perform clock recovery from user-supplied QSFP/QSFP+ modules,
and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTY
transceiver.
The system controller configures SI5328B U57 in free-run mode or automatically switches
over to one of two recovered clock inputs for synchronous operation. Enabling the jitter
attenuation feature requires additional user programming from FPGA IP through the I²C
bus. The jitter attenuated clock circuit is shown in
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Chapter 3: Board Component Descriptions
Figure
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3-9.
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