Vcu118 Fpga U1 Gty Transceiver Bank 233 Connections - Xilinx VCU118 User Manual

Table 3-20: VCU118 FPGA U1 GTY Transceiver Bank 233 Connections
MGT FPGA
(U1) Pin FPGA (U1) Pin Name Schematic Net Name
Bank
G5 MGTYTXP0_233
G4 MGTYTXN0_233
K2 MGTYRXP0_233
K1 MGTYRXN0_233
F7 MGTYTXP1_233
F6 MGTYTXN1_233
H2 MGTYRXP1_233
H1 MGTYRXN1_233
E5 MGTYTXP2_233
GTY
E4 MGTYTXN2_233
Bank
F2 MGTYRXP2_233
233
F1 MGTYRXN2_233
C5 MGTYTXP3_233
C4 MGTYTXN3_233
D2 MGTYRXP3_233
D1 MGTYRXN3_233
L9 MGTREFCLK0P_233
L8 MGTREFCLK0N_233
J9 MGTREFCLK1P_233
J8 MGTREFCLK1N_233
Notes:
1. Ensure that the GTY RefClock being sourced into the RefClock SMAs (J32, J33) is AC coupled for proper clocking operation of
GTY transceivers. Use inline SMA DC blocking capacitors if frequency source output is not AC coupled.
For additional information on GTY transceivers, see UltraScale Architecture GTY Transceivers
User Guide (UG578)
Product Guide (PG182)
For additional information about the quad small form factor pluggable (28 Gb/s QSFP+)
module, see the SFF-8663 specification for the 28 Gb/s QSFP+ at the SFF-8663 specification
website [Ref 24].
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
FIREFLY_TX1_P
FIREFLY_TX1_N
FIREFLY_RX1_P
FIREFLY_RX1_N
FIREFLY_TX2_P
FIREFLY_TX2_N
FIREFLY_RX2_P
FIREFLY_RX2_N
FIREFLY_TX3_P
FIREFLY_TX3_N
FIREFLY_RX3_P
FIREFLY_RX3_N
FIREFLY_TX4_P
FIREFLY_TX4_N
FIREFLY_RX4_P
FIREFLY_RX4_N
MGT_SI570_CLOCK3_C_P
MGT_SI570_CLOCK3_C_N
MGT232_CLK1_P
MGT232_CLK1_N
[Ref 6]. Also see UltraScale FPGAs Transceivers Wizard LogiCORE IP
[Ref 7].
www.xilinx.com
Chapter 3: Board Component Descriptions
Connected Connected Pin
Pin Name
A3
A2
B17
B18
B3
B2
A17
A18
A6
A5
B14
B15
B6
B5
A14
A15
15
16
(1)
J33
(1)
J32
Connected
Device
TX1P
TX1N
RX1P
RX1N
TX2P
TX2N
RX2P
RX2N
QSFP2 U123
TX3P
TX3N
RX3P
RX3N
TX4P
TX4N
RX4P
RX4N
Q3_P
U104 SI53340
clock buffer
Q3_N
1
SMA Connectors
J33(P), J32(N)
1
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