Vcu118 Fpga U1 Gty Transceiver Bank 224 Connections - Xilinx VCU118 User Manual

Quad 233:
• MGTREFCLK0 - MGT_SI570_CLOCK3_C_P/N (U104)
• MGTREFCLK1 - MGT233_CLK1_P/N (SMA J33 P, J32 N)
• Four GTY transceivers allocated to FIREFLY (J6)
Table 3-14 through
227, 231, 232 and 233 connections, respectively.
Table 3-14: VCU118 FPGA U1 GTY Transceiver Bank 224 Connections
FPGA
MGT FPGA (U1) Pin
(U1)
Bank Name
Pin
BE5 MGTYTXP0_224
BE4 MGTYTXN0_224
BB2 MGTYRXP0_224
BB1 MGTYRXN0_224
BC5 MGTYTXP1_224
BC4 MGTYTXN1_224
AY2 MGTYRXP1_224
AY1 MGTYRXN1_224
BA5 MGTYTXP2_224
GTY
BA4 MGTYTXN2_224
Bank
AV2 MGTYRXP2_224
224
AV1 MGTYRXN2_224
AW5 MGTYTXP3_224
AW4 MGTYTXN3_224
AT2 MGTYRXP3_224
AT1 MGTYRXN3_224
AR9 MGTREFCLK0P_224
AR8 MGTREFCLK0N_224
AN9 MGTREFCLK1P_224
AN8 MGTREFCLK1N_224
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Table 3-20 list the VCU118 FPGA U1 GTY transceiver bank 224, 225, 226,
Schematic Net
Name
PCIE_TX15_P
PCIE_TX15_N
PCIE_RX15_P
PCIE_RX15_N
PCIE_TX14_P
PCIE_TX14_N
PCIE_RX14_P
PCIE_RX14_N
PCIE_TX13_P
PCIE_TX13_N
PCIE_RX13_P
PCIE_RX13_N
PCIE_TX12_P
PCIE_TX12_N
PCIE_RX12_P
PCIE_RX12_N
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Chapter 3: Board Component Descriptions
Connected Pin
Connected Pin
Name
A80 HSIP(15)
A81 HSIN(15)
B78 HSOP(15)
B79 HSON(15)
A76 HSIP(14)
A77 HSIN(14)
B74 HSOP(14)
B75 HSON(14)
A72 HSIP(13)
A73 HSIN(13)
B70 HSOP(13)
B71 HSON(13)
A68 HSIP(12)
A69 HSIN(12)
B66 HSOP(12)
B67 HSON(12)
NC
NC
NC
NC
Connected
Device
PCIe EDGE Conn.
U2
61
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