Rld3 Component Memory - Xilinx VCU118 User Manual

RLD3 Component Memory

[Figure 2-1, callout 5]
The 288 MB RLD3 72-bit wide component memory system is comprised of two 36-bit 1.125
Gb RLDRAM3 devices (Micron MT44K32M36RB-083E) located at U141-U142. This memory
system is connected to the XCVU9P HP banks 46, 47, and 48. The RLD3 0.6V VTT termination
voltage (net RLD3_C3_VTT) is sourced from TI TPS51200DR linear regulator U143. The RLD3
memory interface bank VREF pins are not connected, which, coupled with an XDC
set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The
connections between the RLD3 component memories and XCVU9P banks 46, 47, and 48 are
listed in Table
Table 3-4: RLD3 Memory 72-bit I/F to FPGA U1 Banks 46, 47, and 48
FPGA
Schematic Net Name
(U1) Pin
H39 RLD3_C3_72B_DQ0
H40 RLD3_C3_72B_DQ1
G40 RLD3_C3_72B_DQ2
F40 RLD3_C3_72B_DQ3
H38 RLD3_C3_72B_DQ4
G38 RLD3_C3_72B_DQ5
K37 RLD3_C3_72B_DQ6
J37 RLD3_C3_72B_DQ7
F38 RLD3_C3_72B_DQ8
J35 RLD3_C3_72B_DQ9
H35 RLD3_C3_72B_DQ10
J36 RLD3_C3_72B_DQ11
H37 RLD3_C3_72B_DQ12
H34 RLD3_C3_72B_DQ13
G35 RLD3_C3_72B_DQ14
F35 RLD3_C3_72B_DQ15
F36 RLD3_C3_72B_DQ16
G36 RLD3_C3_72B_DQ17
E37 RLD3_C3_72B_DQ18
E38 RLD3_C3_72B_DQ19
C39 RLD3_C3_72B_DQ20
B40 RLD3_C3_72B_DQ21
A39 RLD3_C3_72B_DQ22
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
3-4.
I/O Standard
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Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
D11 DQ0
E10 DQ1
C8 DQ2
C10 DQ3
C12 DQ4
B9 DQ5
B11 DQ6
A8 DQ7
A10 DQ8
J10 DQ9
K11 DQ10
K13 DQ11
L8 DQ12
L10 DQ13
L12 DQ14
M9 DQ15
M11 DQ16
N8 DQ17
D3 DQ18
E4 DQ19
C6 DQ20
C4 DQ21
C2 DQ22
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Ref. Des.
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
U141
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