10/100/1000 Mb/S Tri-Speed Ethernet Phy; Fpga U1 To Ethernet Phy U7 Connections - Xilinx VCU118 User Manual

10/100/1000 Mb/s Tri-Speed Ethernet PHY

[Figure 2-1, callout 19]
The VCU118 evaluation board uses the TI PHY device DP83867ISRGZ (U7) for Ethernet
communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only.
The PHY connection to a user-provided Ethernet cable is through RJ-45 connector J10, a
Wurth 7499111221A with built-in magnetics and status LEDs.
On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY
address[4:0] = 00011.
Table 3-25 lists the FPGA U1 to U7 DP83867ISRGZ Ethernet PHY connections.
Table 3-25: FPGA U1 to Ethernet PHY U7 Connections
FPGA (U1)
Pin
AR23
AV23
AR24 PHY1_PDWN_B_I_INT_B_O
AV21
AU21
AV24
AU24
AU22
AT22
BA21
AR22
AU23
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Net Name
PHY1_MDIO
PHY1_MDC
PHY1_SGMII_IN_N
PHY1_SGMII_IN_P
PHY1_SGMII_OUT_N
PHY1_SGMII_OUT_P
PHY1_SGMII_CLK_N
PHY1_SGMII_CLK_P
PHY1_RESET_B
PHY1_GPIO_0
PHY1_CLKOUT
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Chapter 3: Board Component Descriptions
I/O Standard
Pin
LVCMOS18 17
LVCMOS18 16
LVCMOS18 44
LVCMOS18 28
LVCMOS18 27
LVCMOS18 36
LVCMOS18 35
LVCMOS18 34
LVCMOS18 33
LVCMOS18 43
LVCMOS18 39
LVCMOS18 18
DP83867ISRGZ U7
Name
MDIO
MDC
INT_PWDN
TX_D1_SGMII_SIP
TX_D0_SGMII_SIN
RX_D3_SGMII_SON
RX_D2_SGMII_SOP
RX_D1_SGMII_CON
RX_D0_SGMII_COP
RESET_B
GPIO_2
CLK_OUT
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