Vcu118 Fpga U1 Gty Transceiver Bank 231 Connections - Xilinx VCU118 User Manual

Table 3-18: VCU118 FPGA U1 GTY Transceiver Bank 231 Connections
FPGA
MGT FPGA (U1) Pin Name Schematic Net Name Connected
(U1)
Bank
Pin
V7 MGTYTXP0_231
V6 MGTYTXN0_231
Y2 MGTYRXP0_231
Y1 MGTYRXN0_231
T7 MGTYTXP1_231
T6 MGTYTXN1_231
W4 MGTYRXP1_231
W3 MGTYRXN1_231
P7 MGTYTXP2_231
P6 MGTYTXN2_231
GTY
V2 MGTYRXP2_231
Bank
V1 MGTYRXN2_231
231
M7 MGTYTXP3_231
M6 MGTYTXN3_231
U4 MGTYRXP3_231
U3 MGTYRXN3_231
W9 MGTREFCLK0P_231
W8 MGTREFCLK0N_231
U9 MGTREFCLK1P_231
U8 MGTREFCLK1N_231
A4 MGTRREF_RN
A5 MGTAVTTRCAL_RN
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
QSFP1_TX1_P
QSFP1_TX1_N
QSFP1_RX1_P
QSFP1_RX1_N
QSFP1_TX2_P
QSFP1_TX2_N
QSFP1_RX2_P
QSFP1_RX2_N
QSFP1_TX3_P
QSFP1_TX3_N
QSFP1_RX3_P
QSFP1_RX3_N
QSFP1_TX4_P
QSFP1_TX4_N
QSFP1_RX4_P
QSFP1_RX4_N
QSFP_SI570_CLOCK_C_P
QSFP_SI570_CLOCK_C_N
SI5328_CLOCK1_C_P
SI5328_CLOCK1_C_N
MGTRREF_231
MGTAVTT_FPGA
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Chapter 3: Board Component Descriptions
Connected Pin
Pin Name
36 TX1P
37 TX1N
17 RX1P
18 RX1N
3 TX2P
2 TX2N
22 RX2P
21 RX2N
33 TX3P
34 TX3N
14 RX3P
15 RX3N
6 TX4P
5 TX4N
25 RX4P
24 RX4N
4 OUT
5 OUT_B
28 CLKOUT1_P
29 CLKOUT1_N
R1326.1 100Ω 1% P/U to MGTAVTT_FPGA
NA NA
Send Feedback
Connected
Device
QSFP1 U145
2
U38 SI570 I C
prog. osc.
U57 SI5328B
jitter atten.
NA
65