Left Side Quads - Xilinx VCU118 User Manual

Left Side Quads

The seven GTY quads on the left side of the VCU118 board have connectivity as listed here:
Quad 224:
• MGTREFCLK0 - not connected
• MGTREFCLK1 - not connected
• Four GTY transceivers allocated to PCIe lanes 15:12
Quad 225:
• MGTREFCLK0 - PCIE_CLK1_P/N (U20)
• MGTREFCLK1 - MGT_SI570_CLOCK1_C_P/N (U104)
• Four GTY transceivers allocated to PCIe lanes 11:8
Quad 226:
• MGTREFCLK0 - MGT226_CLK0_P/N (SMA J31 P, J30 N)
• MGTREFCLK1 - not connected
• Four GTY transceivers allocated to PCIe lanes 7:4
Quad 227:
• MGTREFCLK0 - PCIE_CLK2_P/N (U20)
• MGTREFCLK1 - not connected
• Four GTY transceivers allocated to PCIe lanes 3:0
Quad 231:
• MGTREFCLK0 - QSFP_SI570_CLOCK_C_P/N (U38)
• MGTREFCLK1 - SI5328_CLOCK1_C_P/N (U57)
• Four GTY transceivers allocated to QSFP1 (U145)
Quad 232:
• MGTREFCLK0 - MGT_SI570_CLOCK2_C_P/N (U104)
• MGTREFCLK1 - SI5328_CLOCK2_C_P/N (U57)
• Four GTY transceivers allocated to QSFP2 (U123)
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Chapter 3: Board Component Descriptions
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