Vcu118 Fpga U1 Gty Transceiver Bank 232 Connections - Xilinx VCU118 User Manual

Table 3-19: VCU118 FPGA U1 GTY Transceiver Bank 232 Connections
FPGA
MGT
(U1) FPGA (U1) Pin Name Schematic Net Name
Bank
Pin
L5 MGTYTXP0_232
L4 MGTYTXN0_232
T2 MGTYRXP0_232
T1 MGTYRXN0_232
K7 MGTYTXP1_232
K6 MGTYTXN1_232
R4 MGTYRXP1_232
R3 MGTYRXN1_232
J5 MGTYTXP2_232
GTY
J4 MGTYTXN2_232
Bank
P2 MGTYRXP2_232
232
P1 MGTYRXN2_232
H7 MGTYTXP3_232
H6 MGTYTXN3_232
M2 MGTYRXP3_232
M1 MGTYRXN3_232
R9 MGTREFCLK0P_232
R8 MGTREFCLK0N_232
N9 MGTREFCLK1P_232
N8 MGTREFCLK1N_232
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Connected
QSFP2_TX1_P
QSFP2_TX1_N
QSFP2_RX1_P
QSFP2_RX1_N
QSFP2_TX2_P
QSFP2_TX2_N
QSFP2_RX2_P
QSFP2_RX2_N
QSFP2_TX3_P
QSFP2_TX3_N
QSFP2_RX3_P
QSFP2_RX3_N
QSFP2_TX4_P
QSFP2_TX4_N
QSFP2_RX4_P
QSFP2_RX4_N
MGT_SI570_CLOCK2_C_P
MGT_SI570_CLOCK2_C_N
SI5328_CLOCK2_C_P
SI5328_CLOCK2_C_N
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Chapter 3: Board Component Descriptions
Connected Pin
Pin Name
36 TX1P
37 TX1N
17 RX1P
18 RX1N
3 TX2P
2 TX2N
22 RX2P
21 RX2N
33 TX3P
34 TX3N
14 RX3P
15 RX3N
6 TX4P
5 TX4N
25 RX4P
24 RX4N
13 Q2_P
14 Q2_N
35 CLKOUT2_P
34 CLKOUT2_N
Send Feedback
Connected
Device
QSFP2 U123
U104 SI53340
clock buffer
U57 SI5328B
jitter atten.
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