Ddr4 Memory 80-Bit I/F C2 To Fpga U1 Banks 40, 41, And 42 - Xilinx VCU118 User Manual

Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont'd)
FPGA (U1)
Schematic Net Name
Pin
G13 DDR4_C1_BA1
H13 DDR4_C1_BG0
H14 DDR4_C1_A14_WE_B
H15 DDR4_C1_A15_CAS_B
F15 DDR4_C1_A16_RAS_B
F14 DDR4_C1_CK_T
E14 DDR4_C1_CK_C
A10 DDR4_C1_CKE
E13 DDR4_C1_ACT_B
G10 DDR4_C1_PAR
C8 DDR4_C1_ODT
F13 DDR4_C1_CS_B
R17 DDR4_C1_ALERT_B
N20 DDR4_C1_RESET_B
A20 DDR4_C1_TEN
The connections between the C2 80-bit interface DDR4 component memories (U135-U139)
and XCVU9P banks 40, 41, and 42 are listed in
Table 3-3: DDR4 Memory 80-bit I/F C2 to FPGA U1 Banks 40, 41, and 42
FPGA (U1)
Schematic Net Name
Pin
BD30 DDR4_C2_DQ0
BE30 DDR4_C2_DQ1
BD32 DDR4_C2_DQ2
BE33 DDR4_C2_DQ3
BC33 DDR4_C2_DQ4
BD33 DDR4_C2_DQ5
BC31 DDR4_C2_DQ6
BD31 DDR4_C2_DQ7
BA32 DDR4_C2_DQ8
BB33 DDR4_C2_DQ9
BA30 DDR4_C2_DQ10
BA31 DDR4_C2_DQ11
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
I/O Standard
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
SSTL12_DCI
LVCMOS12
SSTL12_DCI
Table
I/O Standard
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
POD12_DCI
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Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
N8 BA1
M2 BG0
L2 WE_B/A14
M8 CAS_B_A15
L8 RAS_B/A16
K7 CK_T
K8 CK_C
K2 CKE
L3 ACT_B
T3 PAR
K3 ODT
L7 CS_B
P9 ALERT_B
P1 RESET_B
N9 TEN
3-3.
Component Memory
Pin # Pin Name
G2 DQL0
F7 DQL1
H3 DQL2
H7 DQL3
H2 DQL4
H8 DQL5
J3 DQL6
J7 DQL7
A3 DQU0
B8 DQU1
C3 DQU2
C7 DQU3
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Ref. Des.
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
U60-U64
Ref. Des.
U135
U135
U135
U135
U135
U135
U135
U135
U135
U135
U135
U135
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