Introduction; I/O - HP Integrity rx6600 User's & Service Manual

Introduction

I/O

I/O
The primary purpose of the CIOBP board is to extend I/O from the PB board's core electronics complex
through HP-proprietary high-speed ropes links. Local I/O bridges receive these ropes in 18-line
signal-bundles, known as rope-bundles, as upstream input and provide PCI/PCI-X interface buses as output
to downstream I/O card adapters. The PCI/PCI-X interfaces are classified under two major categories: public
and private.
Public interfaces are those which connect to PCI slot connector(s) that are left available to the customer to
elect-based on their application needs-the I/O-card adapters which they wish to install, granted the public
slot populated supports said adapter. Private interfaces are predestined, or predefined, to live-out a life in the
service of core-IO. Core-IO is comprised of two species, fast-core and slow-core, also known as the UCIO
(Unified Core-I/O). There are a total 8 public slots (PCI-X mode1/2), 2 private fast-core slots (PCI-X mode1),
and 1 private slow-core UCIO slot (PCI 32-bit/33MHz). The eight public slots are further subdivided into
three speed/bandwidth configurations: 4 PDHP (public dual hot-pluggable), which operate at 64-bit/66MHz
PCI-X; 2 PSHP-SDR (public single hot-pluggable - single data rate), operating at 64-bit/133MHz PCI-X; and 2
PSHP-DDR (public single hot-pluggable - double data rate), at 64-bit/266MHz (133MHz double clocked)
PCI-X mode2. All public slots support HP-server traditional OL* hot-pluggable operations. The private slots
and UCIO are not hot-pluggable. PDHP slots rely on the facilities of DHPC (dual hot-pluggable controller)
FPGAs to enable OL* hot-plug functionality. See Table 1-1 on page 21 for details.
In addition, the CIOBP serves as home to several independent subsystems, namely PDH (SB),
manageability/UCIO (iLO 2 MP, BMC), PRS (power-on reset sequencer), and FSC (fan speed control). Beyond
these subsystems, the CIOBP hosts other circuits; among these are: PCI interface to core-LAN & core-SCSI
fast-core cards, PCI hotplug circuitry, PDH-monitor interface entry-point, scan utility interface entry-point,
Common Doorbell Board (CDB) interface entry-point, bus-switches and DHPCs for PDHP-slot hot-pluggable
functionality, TPM interface entry-point, "Tower of Power" (TOP) interface entry-point, and several
non-isolated POLs for 12-volt power conversion to local rail voltages.
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Chapter 1