Power Subsystem (Bps And I/O Vrm); Power Subsystem Behavior - HP Integrity rx6600 User's & Service Manual

Troubleshooting

Power Subsystem (BPS and I/O VRM)

• One LBA chip uses a single rope interface (used by core I/O) to support a single 32-bit PCI slot running @
33 MHz;
• Three LBA chips use a single-rope interface (one used by core I/O and two are for customer use) to support
dual 64-bit PCI-X slots running @ 66 MHz;
• Two LBA chips use dual-rope (4 ropes total) interfaces (both are for customer use) to support two single
64-bit PCI-X slots running @ 133 MHz;
• Two LBA chips use two quad-rope (8 ropes total) interfaces (both are for customer use) to support two
single 64-bit PCI-X slots running @ 266 MHz.
Power Subsystem (BPS and I/O VRM)
The two bulk power supply FRUs shared by both the chassis provides N+1 redundancy for their chassis. Each
power supply FRU is identified by the chassis as 0 and 1 for logging purposes only as there are no LEDs on
the diagnostic LED panel for these external FRUs.
Power supply FRU failures are identified visually by a single green LED that is turned off when one or both of
the power supplies fail; logged as an IPMI event by voltage sensor logic; and identified as a power supply FRU
failure by the BMC turning on the appropriate LEDs on the front LED panel.
The I/O VRM FRU, located beside the core I/O board FRU, provides all I/O subsystem dc power.

Power Subsystem Behavior

Each bulk power supply FRU provides 1600 Watts of dc power from a nominal 240 VAC 50-60 Hz. The
baseboard management controller (BMC) chip located on the Unified Core I/O board FRU controls the flow of
+12 VDC power to the server's FRUs. (Note that you can both control and display power supply status
remotely with the iLO 2 MP pc and ps commands, respectively.)
Typical power up sequence of the server is as follows:
• Power LED on front panel glows steady Amber when one or two bulk power supplies are plugged into
nominal ac voltage and the +3.3 VDC housekeeping voltage comes on and stays on whenever ac power is
present.
• The BMC, iLO 2 MP, Flash memory, and chassis intrusion circuits are reset after the +3.3 VDC
housekeeping voltage stabilizes.
• The BMC monitors the power button on the front panel.
• When the power button is pressed or when a Wake-on-LAN (WOL) signal is asserted, the BMC signals the
bulk power supplies to fully power up.
• +12 VDC comes up and all of the cooling fans and the various VRMs come up sequentially.
• The BMC signals when the server is ready to come out of reset (clocks are programmed and stable, etc.).
• The server is brought out of reset.
• The Zx2 chip resets all components connected and the server begins the boot process.
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Chapter 5