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PCI-946-1 and P3S440BX Technical Reference manual
3.3.2. Register X91h: Reset History & CPU Fault
Used by the BIOS at runtime; do not write to this register.
Reset history
* = Active low signal
3.3.3. Register x92h: Clearing Reset History & Lock for Watchdog
Not used by the BIOS.
Reset history
Programmable watchdog
* = Active low signal
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Bit
7
6
Reset
Read
PBRES
Write
PBRES
This bit is set when the reset button is pressed. It is cleared at power-
up and when the bit CLRHIS* is "0" (see register x92h description).
WDO
This bit is set when a reset is produced by the watchdog. It is cleared
at power-up and when the bit CLRHIS* is "0" (see register x92h
description).
Bit
7
6
Reset
Read
Write
A 0-1 pulse will clear all reset history bits (refer to the x91h register
CLRHIS
*
described previously). In normal operation, always keep the
CLRHIS* bit to "1" otherwise the reset source will not be captured
(the history latch are disabled when CLRHIS* is "0").
When set, the state of the enable bit for the programmable watchdog
LOCK
(WDEN) cannot be changed.
5
4
3
WDO
5
4
3
3-6
2
1
0
2
1
0
1
1
LOCK
CLRHIS*
LOCK
CLRHIS*
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