Sony HDW-750 Maintenance Manual page 90

1-26. Circuit Description
1-26-5. System Control
SS-92 board
IC1 is SS CPU, and the ROM (IC8 : FLASH MEMORY)
program is developed to the SDRAM (IC6 and IC33) and
the following processes are executed on a RAM basis.
At the same time, the system control can be started from
the external ROM through CN3.
. Connection with EEPROM
The EEPROM (IC403) on the MDC-13 board is connected to
the SS CPU (IC1 : 28_SITXO to 30_SICKO) using synchro-
nous serial communication. Various hours meter data and ser-
vo adjustment values are saved in the EEPROM (IC403).
. Connection with the DVP-18 Board (Video Processor Control)
The DVP-18 board is controlled mainly by the address bus
and the data bus that are shared with the ROM (IC8) and
SDRAM (IC6 and IC33).
Selection of the respective IC chips is performed by decod-
ing the address of A2 to A8. Data to the respective ICs is
sent with the common use of 8 bits of D0 to D7. The com-
munication method is the clock synchronous type and the
clock signal is output from the SS CPU (IC1 : 31_HCLK)
via IC10. IC11 and IC12 are used for the communication
timing signal and for the PIO control. In addition to the
above signals, the following signals are used for connecting
the SS-92 board with the DVP-18 board.
. Input and Reference of the frame signal : CN102 pin-49
. Input and Reference of the color framing signal :
. Output and Frame pulse for ADAM-s : CN102 pin-40
. Output and Frame pulse for ADAM-s : CN102 pin-39
. Asynchronous serial communication
The SS CPU (IC1) has three asynchronous serial connec-
tion channels.
. GPS unit connection :
. PC debug monitor connection : (25-TXD0 and 27-RXD0)
. Remote control connection :
The remote controller is connected to the 8-pin REMOTE
terminal and is sent to the SS-92 board via the AT-143 board.
. Synchronous serial communication
The SS-92 board has two groups of synchronous serial
communication that are used to establish communication
with the total five blocks.
1) Connection with AT-143 board and FP-121 board (IC1
: 214_SIN1, 215_SOUT1, 216_SCK1)
Connection with the camera block is performed
through the AT-143 board. Connection of the audio
data, the LCD display data, and the POWER ON/OFF
related data, is performed through the FP-121 board.
Selection of communication is performed by CN102
(pin-28 and pin-101) of the SS-92 board. The follow-
ing signals are supported by connection with the FP-
121 board after passing through CN102.
. Output, Reference of frame signal :
. Output, SS RESET signal :
. Output, For rewriting the FP CPU ROM : pin-107
1-74
CN102 pin-48
(20-TXD1 and 22-RXD1)
(32-TXD3 and 33-RXD3)
pin-103
pin-104
2) Connection with EQ-88 board and CCM-45 board (IC1
: 278_SIN3, 279_SOUT3, and 280_SCK3)
The REC/PB control is supported by the communica-
tion with the EQ-88 board. The Read/Write control of
the FL-283 printed wiring board (TeleFile) is support-
ed by the communication with the CCM-45 board.
Selection of communication is performed by CN102
(pin-14 and pin-125). In addition, this serial communi-
cation line is used also to write the Config data of
FPGA (IC13) at power-on.
. KY-475 board control
The VTR operation switches (S1 to S5) and the display
LEDs on the KY-475 board are connected directly with the
SS CPU (IC1 : 65_PB15 and 73_PB22) by parallel connec-
tion.
. Timecode
The timecode reader/generator that is built inside the SS
CPU (IC1) is used. The recording LTC from the generator
is delayed by two frames by IC13 of the SS-92 board,
passes through IC23 of the SS-92 board and is sent to the
record amplifier (IC610, Q617, and Q618) of the MDC-13
board. The audio FS signal that is supplied from the DVP-
18 board is used as the reference clock of the delay in
IC13.
IC15 of the SS-92 board is the selector that selects either
the direct output from the generator or the delayed signal
from the MY-99 board (LOOP REC).
IC32 of the SS-92 board is the selector switch that selects
whether the PB timecode from the MDC-13 board is input
to the TC reader of the SS CPU (IC1), or the delayed REC
timecode during LOOP recording is input to the TC reader.
The switch IC32 is used to generate the VITC signal
during LOOP recording.
IC16, IC17 and IC14 of the SS-92 board receive the
external timecode that is input to the TC IN connector
from an external source and waveform-shapes it before
sending it to the SS CPU (IC1).
IC19 on the SS-92 board is the output circuit of the
timecode OUT signal (REC TC and PB TC) that is sup-
plied from the SS CPU (IC1) to feed the timecode signal to
the TC OUT connector.
HDW-750/750CE V1