Camera System (Dcp-28 Board) - Sony HDW-750 Maintenance Manual

1-26-2. Camera System (DCP-28 Board)

DCP-28 board
The DCP-28 board contains the circuit that performs the
camera signal processing, and consists of the following
four blocks.
1) VA block
2) Digital signal processing block
3) Output analog circuit block
4) SG block
1) VA block
The level of the RGB analog video output signal that is
supplied from the PA-253 board is amplified by IC124
to IC126 of this circuit block. (The amplitude factor
changes depending upon the white control and the
master gain settings.)
The multiplication operation of the white shading and
the black shading signals, and addition of the flare
signal are performed in the circuit of IC146 to IC148.
Then the signal receives the Preknee processing so that
the dynamic range of the signal matches that of the A/
D converter circuit.
Finally the bandwidth of the signal is limited to 37
MHz and the output signal is sent to the digital signal
process block.
The VA block performs the black level offset correc-
tion and mixing of the analog test signal in addition to
the above circuit operations.
2) Digital signal processing block
The analog signal that is supplied from the VA block
is sent to the A/D converter (IC188 to IC190) where
the analog signal is converted to the digital signal of
10-bit 74 MHz.
The A/D converted video signal receives the addition
processing of the digital pixels at the adder IC
(IC1017) and is sent to the main digital processor IC
(IC1019).
The digital video signal receives bit expansion in order
to receive non-linear processing to the 10-bit 74 MHz
signal. Then the following processes are performed.
. Various level detections (level detections for Iris,
AWB/ABB, DCC, Trueye, Flare, Area Matrix and
others)
. Linear matrix processing
. Knee (DCC, Tureye) processing
. Gamma processing
. Generation and addition of DTL and APT signals
. White clip and black clip
. Color bar signal generation
HDW-750/750CE V1
The video signal that has received the above digital
processes, is converted to the 10-bit 74 MHz Y-signal
and the decoded color difference signals with which
the title signal is mixed at IC2008.
Then the 10-bit 74 MHz Y-signal and the decoded
color difference signals are sent to the VTR block and
to the camera output block. IC2008 acts as a bilateral
interface with the VTR in order to support the play-
back operation of the VTR.
In addition to the above-described functions, IC2008
performs the following processes.
. Signal detection processing
. Sync signal generation (for the DC-110/110A
board and character IC)
. Mixing and selection of the marker
. Digital Audio Delay (for the DC-110/110A board)
The following four digital signals are prepared as the
camera output signal and are D/A converted by IC201,
IC206, IC211, IC212 and then sent to the output
analog circuit block.
. Y (10-bit 74 MHz)
. R-Y (10-bit 37 MHz)
. B-Y (10-bit 37 MHz)
. VF DTL (8-bit 74 MHz)
3) Output analog circuit block
The D/A converted signal passes through the post
filter, is added by the sync signal at IC802, IC804 and
IC806, and is divided into the three outputs of compo-
nent output, TEST OUT and VF output.
Either the SD signal (down-converted standard signal)
supplied from the DC-110/110A board or the TEST
OUT/VF signal is selected by IC809 and IC810.
The zebra signal and marker are added to the VF
signal at the circuit of Q804 to Q813, Q816, Q819 to
Q821, IC827 and IC828 before the VF signal is output
to VF.
This block also contains the zebra level detection
circuit for HD and SD respectively.
4) SG block
The SG block generates the sync signal to generate the
HD signal and the various clamp and blanking pulses
to be used in the sync and analog circuit. These signals
are generated from the 74 MHz clock signal that is
supplied from the CCD block.
The SG block has the sync separators for the HD and
SD respectively in order to establish GENLOCK. The
SG block can be locked by automatic HD/SD detec-
tion.
1-26. Circuit Description
1-26-2. Camera System
1-65