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I
versus Frequency and Voltage
CC
The I
consumed by the processor is composed of
CC
two components
1 I
The quiescent current that represents inter-
PD
nal device leakage Measured with all inputs at
either V
or ground and no clock applied
CC
2 I
The switching current used to charge and
CCS
discharge internal parasitic capacitance when
changing logic levels I
frequency of operation and the device supply
voltage (V
) I
is given by the formula
CC
CCS
Power
V
I
e
I
e
CCS
Where
V
Supply Voltage (V
e
C
Device Capacitance
e
DEV
f
Operating Frequency
e
Measuring C
on a device like the 80C186EC
PD
would be difficult Instead C
the above formula with I
known V
and frequency Using the C
CC
user can calculate I
at any voltage and frequency
CC
within the specified operating range
Example Calculate typical I
I
I
I
e
a
CC
PD
CCS
0 1 mA
5 2V
0 77
e
a
56 2 mA
e
Parameter
CPD
CPD (Idle Mode)
NOTES
1 Maximum C
is measured at
PD
(or Idle Mode) Due to tester limitations CLKOUT and OSCOUT also have 50 pF loads that increase I
2 Typical C
is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode)
PD
is related to both the
CCS
2
V
C
f
e
DEV
V
C
f
DEV
)
CC
is calculated using
PD
values measured at
CC
value the
PD
at 14 MHz 5 2V V
CC
CC
14 MHz
Typical
0 77
0 55
40 C with all outputs loaded as specified in the AC test conditions and the device in reset
b
80C186EC 188EC 80L186EC 188EC
PDTMR Pin Delay Calculation
The PDTMR pin provides a delay between the as-
sertion of NMI and the enabling of the internal
clocks when exiting Powerdown Mode A delay is
required only when using the on chip oscillator to
allow the crystal or resonator circuit to stabilize
NOTE
The PDTMR pin function does not apply when
RESIN is asserted (i e a device reset while in Pow-
erdown is similar to a cold reset and RESIN must
remain active until after the oscillator has stabilized
To calculate the value of capacitor to use to provide
a desired delay use the equation
440
t
C
(5V 25 C)
c
e
PD
Where
t
desired delay in seconds
e
C
capacitive load on PDTMR in microfarads
e
PD
Example For a delay of 300 ms a capacitor value of
C
440
(300
10
b
e
c
c
PD
Round up to a standard (available) capacitor value
NOTE
The above equation applies to delay time longer
than 10 ms and will compute the TYPICAL capaci-
tance needed to achieve the desired delay A delay
variance of
50% to
a
b
temperature
voltage
and device process ex-
tremes In general higher V
peratures will decrease delay time while lower V
and or higher temperature will increase delay time
Max
Units
1 37
mA V MHz
0 96
mA V MHz
6
0 132 mF is required
e
25% can occur due to
and or lower tem-
CC
CC
Notes
1 2
1 2
by V C F
CC
29
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