System Control Register; Address Assignment Of System Control Registers - Siemens Ertec 400 Manual

SSPIIR/SSPICR
Description SPI interrupt identification register (read)
SPI interrupt clear register (write)
Bit No. Name
0 RIS (Read)
1 TIS (Read)
2 RORIS (Read)
15-3 ---------- (Read)
15-0 ---------- (Write)
4.8

System Control Register

The system control registers are ERTEC 400-specific control registers that can be read and written to from the
PCI/LBU side or from the ARM946. A listing of all system control registers and their address assignments as well
as a detailed description are included in the following sections.
4.8.1

Address Assignment of System Control Registers

The system control registers are 32 bits in width.
Register Name Offset Address Address Area
ID_REG
BOOT_REG
CONFIG_REG
RES_CTRL_REG
RES_STAT_REG
PLL_STAT_REG
CLK_CTRL_REG
PM_STATE_REQ_REG
PM_STATE_ACK_REG
PME_REG
QVZ_AHB_ADR
QVZ_AHB_CTRL
QVZ_AHB_M
QVZ_APB_ADR
QVZ_EMIF_ADR
PCI_RES_REQ
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
R/W
Description
SPI Receive FIFO service request interrupt status
0 = SSPRXINTR is not active
1 = SSPRXINTR is active
SPI Transmit FIFO service request interrupt status
0 = SSPTXINTR is not active
1 = SSPTXINTR is active
SPI Receive FIFO overrun interrupt status
0 = SSPRORINTR is not active
1 = SSPRORINTR is active
Read: Reserved - value is undefined
Write: Receive overrun interrupt is deleted without check to determine
whether data are currently being written.
System Control Registers
0x0000 4 bytes
0x0004 4 bytes
0x0008 4 bytes
0x000C 4 bytes
0x0010 4 bytes
0x0014 4 bytes
0x0018 4 bytes
0x001C 4 bytes
0x0020 4 bytes
0x0024 4 bytes
0x0028 4 bytes
0x002C 4 bytes
0x0030 4 bytes
0x0034 4 bytes
0x0038 4 bytes
0x003C 4 bytes
Addr.: 0x4000_2214
(Base address 0x4000_2600)
Access Default
R 0x40260100
R 0x----
R 0x----
W/R 0x00000100
R 0x00000004
R/W 0x00070005
W/R 0x00000001
R 0x00000000
R/W 0x00000000 Current power state of ERTEC 400
R/W 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
R/W 0xFFFF0002
Page
56
Default: 0x0000
Description
ID ERTEC 400
Boot mode pins Boot[0:2]
ERTEC 400 config pins
Config[0:4]
Control register for reset of
ERTEC 400
Status register for reset of
ERTEC 400
Status register for PLL/FIQ3
Control register for clock of
ERTEC 400
Required power state of the PCI
host
Power management event PME
Address of incorrect addressing on
multilayer AHB
Control signals of incorrect
addressing on multilayer AHB
Master detection of incorrect
addressing on multilayer AHB
Address of incorrect addressing on
AHB
Address that leads to timeout on
EMIF
Request register for placing a SW
reset request on the PCI bridge
ERTEC 400 Manual
Version 1.2.2