Mode Of Operation Of Timers; Timer Interrupts; Timer Prescaler; Cascading Of Timers - Siemens Ertec 400 Manual

4.3.1

Mode of Operation of Timers

Both timers are deactivated after a reset. The timers are enabled by setting the "RUN/XStop" bit in the
status/control register of the respective timer. The timer then counts downwards from its loaded 32-bit starting
value. When the timer value reaches 0, a timer interrupt is generated. The interrupt can then be evaluated by the
IRQ interrupt controller.
If Reload mode = 0, the timer stops.
If Reload mode = 1, the timer is reloaded with the 32-bit reload value and automatically restarted.
The timer can also be reloaded with the reload value during normal timer function (count value <>0). This occurs
by setting the "LOAD" bit in the status/control register of the timer.
Normally, the timer clock operates at 50 MHz, which is generated by the internal PLL. Each timer can also be
operated with an 8-bit prescaler. This can be used to increase the timer time accordingly.
4.3.2

Timer Interrupts

The timer interrupt is active (High) starting from the point at which the timer value is counted down to 0.
The timer interrupt is deactivated (Low) when the reload value is automatically reloaded or the "LOAD" bit is set
by the user. The interrupt is not reset if the loaded reload value is 0. If the timer is deactivated (Run/XStop = 0),
the interrupt is also deactivated.
If the timer operates in Reload mode without a prescaler, the interrupt is present for only one 50 MHz cycle. This
must be taken into account when assigning the relevant interrupt input (level/edge evaluation).
4.3.3

Timer Prescaler

An 8-bit prescaler is available for each timer. Settings can be made independently for each prescaler. Each
prescaler has its own 8-bit reload register. If the reload value or starting value of the prescaler is 0, prescaling
does not occur. The current prescaler value cannot be read out. In addition, there are no status bits for the
prescalers. The prescalers always run in Reload mode.
4.3.4

Cascading of Timers

If the "Cascading" bit is set, both timers can be cascaded to form one 64-bit timer.
The cascaded timer is enabled via the status/control register of Timer 1. The interrupt of Timer 1 is active. The
interrupt of Timer 0 must be disabled when the timers are cascaded. When prescalers are specified, the prescaler
of Timer 1 is used.
The user must provide for data consistency in the user software when reading out the 64-bit timer.
4.3.5

Address Assignment of Timer 0/1 Registers

The timer registers are 32 bits in width. For read/write access of the timer registers to be meaningful, a 32-bit
access is required. However, an 8-bit or 16-bit access is not intercepted by the hardware.
Register Name Offset Address Address Area
CTRL_STAT0
CTRL_STAT1
RELD0
RELD1
CTRL_PREDIV
RELD_PREDIV
TIM0
TIM1

Table 10: Overview of Timer Registers

Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Timer
(Base Address 0x4000_2000)
0x0000 4 bytes
0x0004 4 bytes
0x0008 4 bytes
0x000C 4 bytes
0x0010 4 bytes
0x0014 4 bytes
0x0018 4 bytes
0x001C 4 bytes
Access Default
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00000000 Control register for both prescalers
R/W 0x00000000 Reload register for both prescalers
R 0x00000000
R 0x00000000
Page
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Description
Control/status register timer 0
Control/status register timer 1
Reload register timer 0
Reload register timer 1
Timer 0 value register
Timer 1 value register
ERTEC 400 Manual
Version 1.2.2