Address Assignment Of Uart 1/2 Registers; Uart 1/2 Register Description; Table 14: Overview Of Uart 1/2 Registers - Siemens Ertec 400 Manual

4.6.1

Address Assignment of UART 1/2 Registers

The UART registers are 8 bits in width.
Register Name Offset Address Address Area
UARTDR
UARTRSR/UARTECR
UARTLCR_H
UARTLCR_M
UARTLCR_L
UARTCR
UARTFR
UARTIIR/UARTICR
UARTILPR
0x0024 - 0x003C
0x0040 - 0x0098
0x009C - 0x00FF

Table 14: Overview of UART 1/2 Registers

4.6.2

UART 1/2 Register Description

UARTDR
(1)
UARTDR
(2)
Description UART data registers
Bit No. Name
7 - 0 -------
NOTE: When data are received, the UARTDR data register must be read out first and then the UARTRSR error
register.
UARTRSR/UARTECR
UARTRSR/UARTECR
Description UART receive status register (read)
UART receive error clear register (write)
Bit No. Name
7 - 0 ------- (Write)
0 FE (Read)
1 PE (Read)
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
UART1
(Base Address 0x4000_2300)
UART2
(Base Address 0x4000_2400)
0x0000 1 byte
0x0004 1 byte
0x0008 1 byte
0x000C 1 byte
0x0010 1 byte
0x0014 1 byte
0x0018 1 byte
0x001C 1 byte
0x0020 1 byte
R/W
R/W
Description
WRITE:
If FIFO is enabled, the written data are entered in the FIFO.
-
If FIFO is disabled, the written data are entered in the Transmit holding register
-
(the first word in the Transmit FIFO).
READ:
If FIFO is enabled, the received data are entered in the FIFO.
-
If FIFO is disabled, the received data are entered in the Receive holding register
-
(the first word in the RECEIVE FIFO).
R/W
(1)
R/W
(2)
Description
Framing errors, parity errors, break errors, and overrun errors are deleted.
Framing error = 1
Parity error = 1
the UARTLCR_H register Bit 2.
Access Default
R/W 0x--
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R/W 0x00
R 0x9-
R/W 0x00
R/W 0x00
Addr.: 0x4000_2300
Addr.: 0x4000_2400
Addr.: 0x4000_2304
Addr.: 0x4000_2404
Received character does not have a valid stop bit
Parity of received character does not match the assigned parity in
Page
48
Description
Read/write data from interface
Receive status register (read)
Error clear register (write)
Line control register high byte
Line control register middle byte
Line control register low byte
Control register
Flag register
Int identification register (read)
Interrupt clear register (write)
IrDA low power counter register
(not supported in ERTEC400)
Reserved
Reserved for test purposes
Reserved for future extension
Default: 0x--
Default: 0x--
Default: 0x00
Default: 0x00
ERTEC 400 Manual
Version 1.2.2