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The figure below shows the structure of the clock unit with the individual input and output clocks.
CONFIG4
CONFIG3
CONFIG0
BYPASS_CLK
100MHz
CLKA
12,5 MHz
(PLL-Bypass: 100MHz)
CLKB
REF_CLK
25/50MHz
CONFIG1
SCAN_CLK(3:0)
(TRACEPKT(3:0))
SCANMODE
Figure 9: Detailed Representation of Clock Unit
5.1.2
PCI Clock Supply
The clock supply of the AHB PCI bridge is implemented using two different clock inputs.
Using the external CLK_PCI pin at a frequency of 33 MHz or 66 MHz.
•
Using the internal CLK_50MHz clock per SW via the CLK_CTRL_REG system control register.
•
After a power-up reset, AHB clock CLK_50MHz is enabled.
5.1.3
LBU Clock Supply
In LBU mode, AHB clock CLK_50MHz is enabled for the LBU clock supply. The clock supply for the LBU is
disabled in PCI mode.
In LBU mode, it is recommended that the AHB clock for the PCI bridge be disabled.
Configuration pin CONFIG2 is used to select PCI or LBU mode.
CONFIG2 = 0
CONFIG2 = 1
5.1.4
JTAG Clock Supply
The clock supply for the JTAG interface is implemented using the JTAG_CLK pin. The frequency range is
between 0 and 10 MHz. The boundary scan and the ICE macro cell of the ARM946E-S are enabled via the JTAG
interface.
5.1.5
Ethernet Interface Clock Supply
In the case of Ethernet ports, there are two interfaces to the PHY blocks:
MII mode
•
RMII mode
•
In RMII mode, the Ethernet ports and the PHYs are supplied by the CLK_50MHz system clock. Communication
between the ERTEC port and the PHYs is synchronous.
In MII mode, the two PHYs are supplied with one 25 MHz PHY clock. The clock for the Ethernet ports of the
ERTEC 400 is supplied by the MII PHYs via the RX_CLK and TX_CLK clock cables.
The clock for the Ethernet ports is enabled/disabled via the clock control register in the IRT switch.
The following figure shows the two different Ethernet modes with the clock supply.
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
PLL_IN
OSC
(12,5 MHz)
MUX
12,5 MHz
Divider
1:4
MUX
Divider
MUX
1:2
3
LBU mode
PCI mode
= 2 Ethernet ports to 2 MII-PHYs
= 4 Ethernet ports to quad RMII-PHY
BYPASS_CLK_IN
0
MUX
1
2
PLL_OUT
(300 MHz)
APLL
CLK_IN
0
MUX
1
Clock
0
Generation
0
MUX
1
Lock-Timer
Lock
1
Power-up
Enable
(650us)
Lock Monitor
Page
64
HCLKEN
HCLKEN-
(ARM9)
Gen.
CLK_ARM
CLK_50
CLK_100
PLL_LOCK_STATE
Clock_unit_v2.ppt
ERTEC 400 Manual
Version 1.2.2
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