Table of Contents
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Contents
1
Introduction ............................................................................................................................9
1.1 Applications of the ERTEC 400 .............................................................................................................. 9
1.2 Features of the ERTEC 400 ................................................................................................................... 9
1.3 Structure of the ERTEC 400................................................................................................................... 10
1.4 ERTEC 400 Package ............................................................................................................................. 11
1.5 Signal Function Description.................................................................................................................... 12
1.5.1
GPIO 0 to 31 and Alternative Functions......................................................................................... 12
1.5.2
JTAG and Debug ........................................................................................................................... 13
1.5.3
Trace Port ...................................................................................................................................... 13
1.5.4
Clock and Reset............................................................................................................................. 13
1.5.5
TEST Pins...................................................................................................................................... 13
1.5.6
EMIF, Boot/Config.......................................................................................................................... 14
1.5.7
PCI/LBU......................................................................................................................................... 16
1.5.8
RMII/MII ......................................................................................................................................... 18
1.5.9
Power Supply................................................................................................................................. 19
2
ARM946E-S Processors ........................................................................................................21
2.1 Structure of ARM946E-S........................................................................................................................ 21
2.2 Description of ARM946E-S .................................................................................................................... 22
2.3 Operating Frequency of ARM946E-S..................................................................................................... 22
2.4 Cache Structure of ARM946E-S............................................................................................................. 22
2.5 Tightly Coupled Memory (TCM) ............................................................................................................. 22
2.6 Memory Protection Unit (MPU)............................................................................................................... 23
2.7 Bus Interface of ARM946E-S ................................................................................................................. 23
2.8 ARM946E-S Embedded Trace Macrocell (ETM9).................................................................................. 23
2.9 ARM Interrupt Controller (ICU) ............................................................................................................... 23
2.9.1
Prioritization of Interrupts ............................................................................................................... 23
2.9.2
Trigger Modes................................................................................................................................ 24
2.9.3
Masking the Interrupt Inputs .......................................................................................................... 24
2.9.4
Software Interrupts for IRQ ............................................................................................................ 24
2.9.5
Nested Interrupt Structure.............................................................................................................. 24
2.9.6
EOI End-Of-Interrupt...................................................................................................................... 24
2.9.7
IRQ Interrupt Sources .................................................................................................................... 25
2.9.8
FIQ Interrupt Sources .................................................................................................................... 25
2.9.9
IRQ Interrupts as FIQ Interrupt Sources ........................................................................................ 25
2.9.10 Interrupt Control Register............................................................................................................... 26
2.9.11 ICU Register Description ............................................................................................................... 27
2.10 ARM946E-S Register ............................................................................................................................. 31
3
Bus System of the ERTEC 400..............................................................................................32
3.1 "Multilayer AHB" Communication Bus .................................................................................................... 32
3.1.1
AHB Arbiter.................................................................................................................................... 32
3.1.2
AHB Master-Slave Coupling .......................................................................................................... 32
3.2 APB I/O Bus ........................................................................................................................................... 33
4
I/O on APB bus .......................................................................................................................33
4.1 BOOT ROM............................................................................................................................................ 33
4.1.1
Booting from External ROM ........................................................................................................... 34
4.1.2
Booting via SPI .............................................................................................................................. 34
4.1.3
Booting via UART1 ........................................................................................................................ 34
4.1.4
Booting via PCI or LBU .................................................................................................................. 34
4.2 General Purpose I/O (GPIO) .................................................................................................................. 35
4.2.1
Address Assignment of GPIO Registers ........................................................................................ 35
4.2.2
GPIO Register Description............................................................................................................. 36
4.3 Timer 0 and Timer 1 ............................................................................................................................... 37
4.3.1
Mode of Operation of Timers ......................................................................................................... 38
4.3.2
Timer Interrupts.............................................................................................................................. 38
4.3.3
Timer Prescaler.............................................................................................................................. 38
4.3.4
Cascading of Timers ...................................................................................................................... 38
4.3.5
Address Assignment of Timer 0/1 Registers.................................................................................. 38
4.3.6
Timer 0/1 Register Description ...................................................................................................... 39
4.4 F - Counter ............................................................................................................................................. 41
4.4.1
Address Assignment of F-Timer Registers .................................................................................... 42
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Page 5
ERTEC 400 Manual
Version 1.2.2
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