Spi Register Description - Siemens Ertec 400 Manual

4.7.2

SPI Register Description

SSPCR0
Description Control register 0. Configuration frame format and baud rate for SPI.
Bit No. Name
3 - 0 DSS
Data Size Select
5 - 4 FRF
Frame Format
6 SPO
Serial Clock Output
Polarity
7 SPH
Phase of
Transmission Bit
15-8 SCR
Serial Clock Rate
SSPCR1
Description Control register 1. Configuration frame format and baud rate for SPI.
Bit No. Name
0 RIE
1 TIE
2 RORIE
3 LBM
4 SSE
5 MS
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
R/W Addr.: 0x4000_2200
Description
0000 Reserved (undefined)
0001 Reserved (undefined)
0010 Reserved (undefined)
0011 4-bit data
0100 5-bit data
0101 6-bit data
0110 7-bit data
0111 8-bit data
00 Motorola SPI frame format
01 TI synchronous serial frame format
02
National Microwire frame format
03 Reserved (undefined operation)
Can only be used in Motorola SPI frame format.
0 Received bits are engaged on the rising edge of SCLKIN/OUT.
Sent bits are switched on the falling edge of SCLKIN/OUT.
1 Received bits are engaged on the falling edge of SCLKIN/OUT.
Sent bits are switched on the rising edge of SCLKIN/OUT.
Can only be used in Motorola SPI frame format.
0 Received MSB is expected after frame signal has gone to Low
1 Received MSB is expected ½ clock cycle after frame signal has gone to Low
The serial clock rate is taken for calculation of the Transmit/Receive bit rate.
The calculation formula is as follows:
F
SSPCLK
----------------------------------------
CPSDVSR x (1 + SCR)
SCR := 1 to 255
CPSDVSR := 2 to 254 (for a description, refer to SSPCPSR Register)
R/W Addr.: 0x4000_2204
Description
Receive FIFO interrupt enable:
0 = Receive FIFO half full or more interrupt SSPRXINTR is disabled
1 = Receive FIFO half full or more interrupt SSPRXINTR is enabled
Transmit FIFO interrupt enable:
0 = Transmit FIFO half full or less interrupt SSPTXINTR is disabled
1 = Transmit FIFO half full or less interrupt SSPTXINTR is enabled
Receive FIFO overrun interrupt enable:
0 = FIFO overrun display interrupt SSPRORINTR is disabled
(When this bit is deleted, the SSPRORINTR interrupt is also deleted if this interrupt
was currently being enabled)
1 = FIFO overrun display interrupt SSPRORINTR is enabled
Loop back mode
0 = Normal serial operation is active
1 = Loop back mode is active. (The output of the Transmit serial shifter is connected
internally to the input of the Receive serial shifter.)
Synchronous serial port enable:
0 = SPI port is disabled
1 = SPI port is enabled
Master/slave mode select
(This bit can only be changed if Bit 4 SSE = 0)
0 = Device is master (default)
1 = Device is slave
Page
Default: 0x0000
1000 9-bit data
1001 10-bit data
1010 11-bit data
1011 12-bit data
1100 13-bit data
1101 14-bit data
1110 15-bit data
1111 16-bit data
Default: 0x0000
54
ERTEC 400 Manual
Version 1.2.2