Table of Contents
Advertisement
Caution:
In case of subsequent block writes from host to PCI target and from the ARM to the PCI bus, write accesses on
the AHB-bus may be executed in an erroneous way under certain circumstances. The following sequence of
writes triggers the behaviour:
1.. A PCI burst write access to the upper data word of a 1k address segment occur (= multiple address of
...03FC in addressable area).
2.A subsequent PCI burst write access to the first data word of the same 1 k segment.
Workaround:
Use one of the following procedures to avoid the error:
1. Do not use burst writes to the first or last data word of the 1k segment.
2. Issue a dummy read or dummy write after a write burst to the last data word of the 1 k segment.
3. Avoid writing to the first data word in the same 1 k segment after a write to the last data word.
The PROFINET stack uses a data location as described in workaround 3. The application software should be
checked by the customer.
8.2
ERTEC 400 Applications with PCI:
ERTEC 400 on a PC card with use of power management functionality
•
ERTEC 400 used with PCI bus as the local bus
•
8.2.1
ERTEC 400 in a PC System
In PC systems, the ERTEC 400 can be integrated into the system as a PC card with host and master
functionality. The PC card can be operated on the 32-bit bus at a maximum of 66 MHz. Interrupt INTB_N must be
disabled because the PC interface of the ERTEC 400 is only a "single function interface." However, in order for a
low-priority interrupt to be interrupted by a high-priority interrupt from the IRT switch, the IRQ0_HP interrupt can
be output on the SERR_N output. In the case of PC processors, this results in an NMI interrupt. Optionally, IRT
interrupt IRQ_IRT_API_ERR can also be placed on the SERR_N output.
Power management support is an additional requirement. In such applications, the PC card can be operated in
different power modes. The PC card is also able to generate certain events in the host system that "wake up" the
host system (WAKE function). If the Wake function is employed for the PC card, it must be ensured that the PC
card can still operate at "reduced" function in power-down state and an interrupt can be generated via the PME_N
output.
The following sequence illustrates the functioning of a power management state:
A power-down state (e.g., D3hot) is requested by the PC host.
•
Interrupt is requested at the local processor.
•
Current state is backed up with the corresponding registers and the requested state is set by the ERTEC
•
400.
PCI interrupts are disabled.
•
Requested state is confirmed.
•
PCI bus is powered down and functions are disabled by the PC host.
•
Data traffic is monitored for a certain event by the ERTEC 400.
•
The "PME" interrupt is triggered when the monitored event is detected.
•
PC host system is powered up when the individual devices request the Power-UP state.
•
Backed-up state is restored by the ERTEC 400.
•
The last state is established in the PC host system.
•
Transition to requested "Power UP" power state occurs.
•
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Page
88
ERTEC 400 Manual
Version 1.2.2
Advertisement
Table of Contents
