Siemens Ertec 400 Manual page 72

Async Bank 0 Config
Async Bank 1 Config
Async Bank 2 Config
Async Bank 3 Config
Description Settings for the timing and the data bus width for accesses via an asynchronous interface
(CS_PER0_N to CS_PER3_N) (AHB clock cycle has a length of 20 ns)
Bit No. Name
31 ----
30 EW
29..26 W_SU
25..20 W_STROBE
19..17 W_HOLD
16..13 R_SU
12..7 R_STROBE
6..4 R_HOLD
3..2 ----
1..0 ASIZE
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
W/R Addr.: 0x7000_0010
W/R Addr.: 0x7000_0014
W/R Addr.: 0x7000_0018
W/R Addr.: 0x7000_001C
Description
Reserved
Extend Wait mode
0: RDY_PER_N = don't care
1: Wait until RDY_PER_N is active
Write strobe setup cycles
(w_su + 1) AHB clock cycles between valid address, data, and chip select
and falling edge of the write signal.
Write strobe duration cycles
(w_strobe + 1) AHB clock cycles between falling and rising edges of the write
signal.
Write strobe hold cycles
(w_hold + 1) AHB clock cycles between rising edge of the write signal and
change of address, data, and chip select.
Read strobe setup cycles
(r_su + 1) AHB clock cycles between valid address and chip select and
falling edge of the read signal (RD_N).
Read strobe duration cycles
(r_strobe + 1) AHB clock cycles between falling and rising edges of the read
signal.
Read strobe hold cycles
(r_hold + 1) AHB clock cycles between rising edge of the read signal and
change of address and chip select.
Reserved
Asynchronous bank size
00: 8-bit data bus
01: 16-bit data bus
1x: 32-bit data bus
Page
72
Default: 0x3FFF_FFF2
Default: 0x3FFF_FFF2
Default: 0x3FFF_FFF2
Default: 0x3FFF_FFF2
ERTEC 400 Manual
Version 1.2.2