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2.2
Description of ARM946E-S
The ARM946E-S processor system is a member of the ARM9 Thumb family. It has a processor core with Harvard
architecture. Compared to the standard ARM9 family, the ARM946E-S has an enhanced V5TE architecture
permitting faster switching between ARM and Thumb code segments and an enhanced multiplier structure. In
addition, the processor has an integrated JTAG interface.
2.3
Operating Frequency of ARM946E-S
The processor can be operated at 50 MHz, 100 MHz, or 150 MHz. The operating frequency is set during the reset
phase via the CONFIG[3] and CONFIG[4] configuration pins. Communication with the components of the ERTEC
400 takes place via the AHB bus at a frequency of 50 MHz.
2.4
Cache Structure of ARM946E-S
The following caches are integrated in the ARM946E-S.
8 Kbytes of instruction cache with lock function
•
4 Kbytes of data cache with lock function
•
Both caches are "Four-Way Set Associative" caches with 1-Kbyte segments. Each segment consists of 32 lines
with 32 bytes (8 x 4 bytes). The D-cache has "write buffers" with write-back function.
The lock function enables the user to lock the contents of the cache segments ("LOCK"). This function enables
the command set for fast routines to be maintained permanently in the instruction cache. This mechanism can
only be implemented on a segment-specific basis in the ARM946E-S.
Both caches are locked after a reset. The caches can be enabled only if the "memory protection unit" is enabled
at the same time.
The I-cache can be enabled by setting Bit 12 of the CP15 control register.
The D-cache can be enabled by setting Bit 2 of the CP15 control register.
Access to this area is blocked if the cache is not enabled.
For more information on caching, refer to Section 3 of /1/.
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document.
2.5
Tightly Coupled Memory (TCM)
A 4-Kbyte data TCM (D-TCM) is implemented in the ARM946E-S processor of the ERTEC 400. The memory is
locked after a reset. The D-TCM can be placed anywhere in the address space of the ARM946E-S and must be
used together with a region of the memory protection unit. Data of fast routines can be placed in the D-TCM.
The D-TCM can be enabled by setting Bit 16 of the CP15 control register.
In addition, the address area of the D-TCM must be set in the Tightly-Coupled Memory register.
For more information on the D-TCM, refer to Section 5 of /1/.
For more information on the description of the ARM946 registers, refer to Section 2.10 of this document.
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Page
22
ERTEC 400 Manual
Version 1.2.2
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