Siemens Ertec 400 Manual page 50

UARTLCR consists of 3 bytes. Writing of bytes is complete when UARTLCR_H has been written. If one of the first
two bytes is to be changed, UARTLCR_H must be written at the end following the change.
Example: Write UARTLCR_L and/or UARTLCR_M, write UARTLCR_H as acceptance.
Write UARTLCR_H only means write and accept UARTLCR_H bits.
UARTCR
(1)
UARTCR
(2)
Description UART control registers
Bit No. Name
0 UARTEN
1 SIREN
2 SIRLP
3 MSIE
4 RIE
5 TIE
6 RTIE
7 LBE
UARTFR
(1)
UARTFR
(2)
Description UART flag registers
Bit No. Name
0 CTS
1 DSR
2 DCD
3 BUSY
4 RXFE
5 TXFF
6 RXFF
7 TXFE
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
R/W Addr.: 0x4000_2314
R/W Addr.: 0x4000_2414
Description
UART Enable = 1 UART Data can be transmitted/received
SIR enable = 1 IrDA SIR Endec is enabled. The bit can only be changed if
UARTEN = 1
IrDA SIR Low power mode
Modem status interrupt enable = 1
Receive interrupt enable = 1
Transmit interrupt enable = 1
Receive timeout interrupt enable = 1
Loop back enable
R Addr.: 0x4000_2318
R Addr.: 0x4000_2418
Description
Clear To Send This bit is the inverse signal of UART input CTS.
Data Set Ready This bit is the inverse signal of UART input DSR.
Data Carrier Detect This bit is the inverse signal of UART input DCD.
UART Busy The bit is set if send data are in progress or if the Transmit FIFO
is not empty.
Receive FIFO Empty = 1 if
FIFO is disabled and Receive holding register is empty
FIFO is disabled and Receive FIFO buffer is empty
Transmit FIFO Full = 1 if
FIFO is disabled and Transmit holding register is full
FIFO is enabled and Transmit FIFO buffer is full
Receive FIFO Full = 1 if
FIFO is disabled and Receive holding register is full
FIFO is enabled and Receive FIFO buffer is full
Transmit FIFO Empty = 1 if
FIFO is disabled and Transmit holding register is empty
FIFO is enabled and Transmit FIFO buffer is empty
Page
Default: 0x00
Default: 0x00
Interrupt is enabled
Receive interrupt is enabled
Transmit interrupt is enabled
Receive timeout interrupt is enabled
Default: 0x9-
Default: 0x9-
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ERTEC 400 Manual
Version 1.2.2