Siemens Ertec 400 Manual page 55

6 SOD
15-7 -------
SSPDR
Description SPI data register
Bit No. Name
15-0 DATA [15:0]
SSPSR
Description SPI status register
Bit No. Name
0 TFE
1 TNF
2 RNE
3 RFF
4 BSY
15-5 ------------
SSPCPSR
Description SPI clock prescale register
Bit No. Name
7 - 0 CPSDVSR
15-5 ------------
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Slave mode output disable
(This bit is only relevant in slave mode MS = 1)
In "Multiple slave systems," the master can send a broadcast message to all slaves in
the system in order to ensure that only one slave drives data at its Transmit output
0 = SPI can drive the SSPTXD output in slave mode
1 = SPI must not drive the SSPTXD output in slave mode
Reserved
Read: Value is undefined
Write: Should always be written with zero
R/W Addr.: 0x4000_2208
Description
Transmit/Receive FIFO
Read = Receive FIFO
Write = Transmit FIFO
(If < 16 bits of data, the user must write the data to the Transmit FIFO in the proper
format. When data are read, they are read out correctly from the Receive FIFO.)
R Addr.: 0x4000_220C
Description
Transmit FIFO empty
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
Transmit FIFO not full
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
Receive FIFO not empty
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
Receive FIFO full
0 = Receive FIFO is not full
1 = Receive FIFO is full
SPI busy flag
0 = SPI is
1 = SPI is sending and/or receiving a frame or the Transmit FIFO is
not empty.
Reserved
Read: Value is undefined
Write: Should always be written with zero
R/W Addr.: 0x4000_2210
Description
Clock prescale divisor
(Value between 2 and 254. For formula, refer to SSPCR0 Register.)
When the value is read, bit 0 is always zero.
Reserved
Read: Value is undefined
Write: Should always be written with zero
Page
Default: 0x----
Default: 0x0000
Default: 0x0000
55
ERTEC 400 Manual
Version 1.2.2