Siemens Ertec 400 Manual page 15

No. Signal Name
79 D0
80 D1
81 D2
82 D3
83 D4
84 D5
85 D6
86 D7
87 D8
88 D9
89 D10
90 D11
91 D12
92 D13
93 D14
94 D15
95 D16
96 D17
97 D18
98 D19
99 D20
100 D21
101 D22
102 D23
103 D24
104 D25
105 D26
106 D27
107 D28
108 D29
109 D30
110 D31
111 WR_N
112 RD_N
113 CS_PER0_N
114 CS_PER1_N
115 CS_PER2_N
116 CS_PER3_N
117 BE0_DQM0_N
118 BE1_DQM1_N
119 BE2_DQM2_N
120 BE3_DQM3_N
121 RDY_PER_N
122 CLK_SDRAM
123 CS_SDRAM_N
124 RAS_SDRAM_N
125 CAS_SDRAM_N
126 WE_SDRAM_N
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Alternative I/O
(5)
Reset (Reset)
Function
EMIF (External Memory Interface)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
B (I)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
O (O)
I (I)
O (O)
O (O)
O (O)
O (O)
O (O)
Pull- Pin No. Comment
up N2 Data bit 0
up P1 Data bit 1
up P2 Data bit 2
up R2 Data bit 3
up T1 Data bit 4
up T2 Data bit 5
up U2 Data bit 6
up V2 Data bit 7
up W1 Data bit 8
up W2 Data bit 9
up Y2 Data bit 10
up AA1 Data bit 11
up W4 Data bit 12
up AA2 Data bit 13
up AB2 Data bit 14
up AA3 Data bit 15
up N6 Data bit 16
up M5 Data bit 17
up N4 Data bit 18
up P5 Data bit 19
up R6 Data bit 20
up R4 Data bit 21
up R5 Data bit 22
up T5 Data bit 23
up V4 Data bit 24
up W5 Data bit 25
up AA4 Data bit 26
up AB4 Data bit 27
up AA5 Data bit 28
up AB5 Data bit 29
up AA6 Data bit 30
up AB6 Data bit 31
AA9 Write strobe
AB9 Read strobe
Chip select bank 1 (ROM);
AB8
boot area
AA7 Chip select bank 2
W6 Chip select bank 3
V6 Chip select bank 4
N1 Byte enable 0 for D(7:0)
V1 Byte enable 1 for D(15:8)
L5 Byte enable 2 for D(23:16)
T4 Byte enable 3 for D(31:24)
up AA8 Ready signal
L2 Clock SDRAM
K2 Chip select SDRAM
K1 RAS line SDRAM
L4 CAS line SDRAM
M2 RD/WR SDRAM
Page
15
ERTEC 400 Manual
Version 1.2.2