System Control Register; Address Assignment Of System Control Registers - Siemens ERTEC200 Manual

SSPIIR/SSPICR
Description SPI interrupt identification register (read)
SPI interrupt clear register (write)
Bit No. Name
0 RIS (Read)
1 TIS (Read)
2 RORIS (Read)
15-3 ---------- (Read)
15-0 ---------- (Write)
4.8

System control register

The system control registers are ERTEC 200-specific control registers that can be read and written to from the individual
AHB masters from the APB bus. For a listing of all system control registers and their address assignments as well as a
detailed description, refer to the following sections.
4.8.1

Address Assignment of System Control Registers

The system control registers are 32 bits in width.
Register Name Offset Address
ID_REG
BOOT_REG
SER_CFG_REG
RES_CTRL_REG
RES_STAT_REG
PLL_STAT_REG
QVZ_AHB_ADR
QVZ_AHB_CTRL
QVZ_AHB_M
QVZ_APB_ADR
QVZ_EMIF_ADR
MEM_SWAP
M_LOCK_CTRL
ARM9_CTRL
ARM9_WE
ERTEC 200_TAG
PHY_CONFIG
PHY_STATUS
Copyright © Siemens AG 2007. All rights reserved.
Technical data subject to change
R/W Addr.: 0x4000_2214
Description
SPI Receive FIFO service request interrupt status
0 = SSPRXINTR is not active
1 = SSPRXINTR is active
SPI Transmit FIFO service request interrupt status
0 = SSPTXINTR is not active
1 = SSPTXINTR is active
SPI Receive FIFO overrun interrupt status
0 = SSPRORINTR is not active
1 = SSPRORINTR is active
Read: Reserved Value is undefined
Write: Receive overrun interrupt is deleted without check to determine
whether data are currently being written.
System Control Registers
Address Area
0x0000 4 bytes
0x0004 4 bytes
0x0008 4 bytes
0x000C 4 bytes
0x0010 4 bytes
0x0014 4 bytes
0x0028 4 bytes
0x002C 4 bytes
0x0030 4 bytes
0x0034 4 bytes
0x0038 4 bytes
0x0044 4 bytes
0x004C 4 bytes
0x0050 4 bytes
0x0054 4 bytes
0x0058 4 bytes
0x005C 4 bytes
0x0060 4 bytes
Default: 0x0000
(Base address 0x4000_2600)
Access Default
R 0x40270100
R Boot-Pins
R Config-Pins
W/R 0x00000004
R 0x00000004
R/W 0x00070005
R 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
R 0x00000000
R/W 0x00000000
R/W 0x00000000
R/W 0x00001939
R/W 0x00000000
R 0x000101xx
R/W 0x00000000
R 0x00000000
58
Description
ID ERTEC 200
Boot mode pins Boot[3:0]
ERTEC 200 config pins
Config[6:1]
Control register for reset of
ERTEC 200
Status register for reset of
ERTEC 200
Status register for PLL/FIQ3
Address of incorrect addressing
on multilayer AHB
Control signals of incorrect
addressing on multilayer AHB
Master detection of incorrect
addressing on multilayer AHB
Address of incorrect addressing
on AHB
Address that leads to timeout on
EMIF
Memory Swapping in Segment 0
on the AHB bus
AHB master lock enable. Master-
selective enable of AHB lock
functionality
Controller of ARM9 and ETM
inputs
Write protection register for
ARM9_CTRL
TAG number of current switching
status
PHY1/PHY2
Configuration registers
PHY1/PHY2
Status registers
ERTEC 200 Manual
Version 1.1.0