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Siemens Ertec 400 Manual

Siemens Ertec 400 Manual

Enhanced real-time ethernet controller
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ERTEC 400
Enhanced Real-Time Ethernet Controller
Manual
Page 1
Copyright © Siemens AG 2010. All rights reserved.
ERTEC 400 Manual
Technical data subject to change
Version 1.2.2

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Summary of Contents for Siemens Ertec 400

  • Page 1 ERTEC 400 Enhanced Real-Time Ethernet Controller Manual Page 1 Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 2 All product and system names are registered trademarks of their respective owner and must be treated as such. Technical data subject to change. Page 2 Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 3 Preface Target Audience of this Manual This manual is intended for hardware developers who want to use the ERTEC 400 for new products. Experience working with processors and designing embedded systems and knowledge of Ethernet are required for this. It describes all ERTEC 400 function groups in detail and provides information that you must take into account when configuring your own PROFINET IO device hardware.
  • Page 4 Fax: (423)- 262- 2103 One Internet Plaza Phone: (423)- 262- 2576 PO Box 4991 E-mail: profibus.sea@siemens.com Johnson City, TN 37602-4991 Page 4 Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 5: Table Of Contents

    Contents Introduction ..........................9 1.1 Applications of the ERTEC 400 ......................9 1.2 Features of the ERTEC 400 ........................9 1.3 Structure of the ERTEC 400........................10 1.4 ERTEC 400 Package ..........................11 1.5 Signal Function Description........................12 1.5.1 GPIO 0 to 31 and Alternative Functions..................12 1.5.2...
  • Page 6 7.2 Page Offset Setting ..........................75 7.3 Page Control Setting ..........................76 7.3.1 LBU Read from ERTEC 400 with separate Read/Write line (LBU_RDY_N active low) ....77 7.3.2 LBU Write to ERTEC 400 with separate Read/Write line (LBU_RDY_N active low)...... 78 7.3.3...
  • Page 7 8.4 PCI Register Description ........................91 Memory Description.......................92 9.1 Memory Partitioning of the ERTEC 400 ....................92 9.2 Detailed Memory Description ......................... 93 Test and Debugging.......................95 10.1 ETM9 Embedded Trace Macrocell ......................95 10.1.1 Trace Modes..........................95 10.1.2 Features of the ETM9 Module ....................... 95 10.1.3 ETM9 Registers ..........................
  • Page 8 Table 19: Setting of Various Page Sizes ....................... 75 Table 20: Setting of Various Offset Areas ......................75 Table 21: Overview of Accesses to Address Areas of ERTEC 400 ............... 76 Table 22: LBU read access timing with seperate Read/Write line ................. 77 Table 23: LBU write access timing with seperate Read/Write line.................

  • Page 9: Introduction

    By virtue of its integrated ARM946 processor, integrated 4-port realtime Ethernet switch, and available options for connecting external host processor systems to a selectable bus system (PCI or LBU), the ERTEC 400 meets all of the requirements for implementing PROFINET devices with integrated switch functionality.

  • Page 10: Structure Of The Ertec 400

    Switch Port1 Port2 Port3 Port4 SM I RM II- Interface REF_CLK PC I-/Local Bus Figure 1: ERTEC 400 Block Diagram Page 10 Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 11: Ertec 400 Package

    ERTEC 400 Package The ERTEC 400 is supplied in an FBGA package with 304 pins. The distance between the pins is 0.8 mm. The package dimensions are 19 mm x 19 mm. Figure 2: ERTEC 400 Package Description The following documents contain the soldering instructions for the ERTEC 400: /10/ Soldering instructions for lead-based block.

  • Page 12: Signal Function Description

    Signal Function Description Pin Description for ERTEC 400 The ERTEC 400 Ethernet communication block is available in a 304-pin FBGA package: The signal names of the ERTEC 400 are described in this section. 1.5.1 GPIO 0 to 31 and Alternative Functions Various signals are multiplexed on the same pin.

  • Page 13: Jtag And Debug

    AA15 1.5.5 TEST Pins Signal Name Pull- Pin No. Comment (Reset) TEST Test mode TEST_N Test configuration TMC1 Test configuration TMC2 Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 14: Emif, Boot/Config

    O (I) configuration (ext. PU/PD necessary) Address bit 23 / ERTEC400 – CONFIG4 (2) O (I) system configuration (ext. PU/PD necessary) Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 15 O (O) Chip select SDRAM RAS_SDRAM_N O (O) RAS line SDRAM CAS_SDRAM_N O (O) CAS line SDRAM WE_SDRAM_N O (O) RD/WR SDRAM Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 16: Pci/Lbu

    B/I (I) LBU: Address Bit 0 DEVSEL_N LBU_AB01 B/I (I) LBU: Address Bit 1 TRDY_N LBU_AB02 B/I (I) LBU: Address Bit 2 Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 17 PCI mode: Open drain; ext. PU INTB_N LBU_IRQ1_N O/O (T) necessary LBU mode: No open drain Selection of 66/33 MHz PCI M66EN B/I (I) clock Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 18: Rmii/Mii

    Port 2 MII: Carrier sense Port 1 RMII: Receive error Port 2 RX_ER_P2 RX_ER_P1 I/I (I) MII: Receive error Port 1 Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 19: Power Supply

    SV Analog PCI 1.5 V (1 pin) AGND_PCI GND Analog PCI (1 pin) TACT_N Not used Table 1: ERTEC 400 Pin Assignment and Signal Description Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 20 Function = Output, I/O function while RESET = Output or I /I Function 1 = Input, Function 2 = Input, I/O function while RESET = Input Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 21: Arm946E-S Processors

    ARM946E-S Processors The ARM946E-S processor is implemented in the ERTEC 400. This description is based on /1/ and /2/. Structure of ARM946E-S An ARM946E-S processor system is used. The figure below shows the structure of the processor. In addition to the processor core, the system contains one data cache, one instruction cache, a memory protection unit (MPU), a system control coprocessor, and a tightly coupled memory.

  • Page 22: Description Of Arm946E-S

    Tightly Coupled Memory (TCM) A 4-Kbyte data TCM (D-TCM) is implemented in the ARM946E-S processor of the ERTEC 400. The memory is locked after a reset. The D-TCM can be placed anywhere in the address space of the ARM946E-S and must be used together with a region of the memory protection unit.

  • Page 23: Memory Protection Unit (Mpu)

    An ETM9 module is connected at the ARM946E-S. This module permits debugging support for data and instruction traces in the ERTEC 400. The module contains all signals required by the processor for the data and instruction traces. The ETM9 module is operated by means of the JTAG interface. The trace information is provided outwards to the trace port via a FIFO memory.

  • Page 24: Trigger Modes

    Each of the two interrupt vector registers can be referenced using two different addresses. The interrupt controller interprets the reading of Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change...

  • Page 25: Irq Interrupt Sources

    Table 3: Overview of FIQ Interrupts (1) Access to non-existing addresses is detected by the individual function groups of the ERTEC 400 and triggers a pulse with duration Tp = 2/50 MHz. For evaluation of this interrupt, the connected FIQ input must be specified as an edge-triggered input.

  • Page 26: 2.9.10 Interrupt Control Register

    0x0070 4 bytes 0x0000000F Priority register 0 PRIOREG 1 0x0074 .... PRIOREG15 0x00AC 4 bytes 0x0000000F Priority register 15 Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 27: 2.9.11 Icu Register Description

    Binary code of input number 31 - 4 Vector ID Valid IRQ vector: always ‘0’. Default vector: always ‘1’ (also bits 3 – 0). Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 28 Inputs 0 to 7 of the FIQ interrupt controller '0' = Fast interrupt request not confirmed '1' = Fast interrupt request has been confirmed Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 29 Name Description 15 – 0 EDGEREG Interrupt input 0 to 15 0=Interrupt detection via positive edge 1=Interrupt detection via negative edge Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 30 Specification of priority of an interrupt request at the associated input Bit No. Name Description 3 – 0 PRIOREG Binary code of the priority Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 31: 2.10 Arm946E-S Register

    When this register is written to, unforeseeable configuration changes can occur in the ARM946. Refer to documents /1/ and /2/ for a detailed description of the ARM946 registers. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change...

  • Page 32: Bus System Of The Ertec 400

    Bus System of the ERTEC 400 The ERTEC 400 has two different buses internally. High-performance communication bus (multilayer AHB bus) I/O bus (APB bus) The following function blocks are connected directly to the multilayer AHB bus: ARM946E-S (Master/Slave) IRT switch...

  • Page 33: Apb I/O Bus

    32 bits and operates at a frequency of 50 MHz. I/O on APB bus The ERTEC 400 block has multiple I/O function blocks. They are connected to the 32-bit APB I/O bus. The ARM946E-S or PCI/LBU interface can access the I/O. The following I/O are available.

  • Page 34: Booting From External Rom

    PCI slave macro is enabled during the boot operation in the ARM946E-S. This enables the user software to be loaded from the PCI master to the various memory areas of the ERTEC 400. At the end of the data transfer, the PCI master sets an identification bit in the SRAM in order to communicate to the ARM processor that the download is complete.

  • Page 35: General Purpose I/O (Gpio)

    "INT_QVZ_PCI_STATE" in register "PLL_STAT_REG" at the beginning of 2nd level boot code. General Purpose I/O (GPIO) A maximum of 32 general purpose inputs/outputs are available in the ERTEC 400. After a reset, these are set as GPIO inputs. GPIOs [31, 7 : 0] are always available as I/O because no additional functions can be assigned.

  • Page 36: Gpio Register Description

    GPIO11_PORT_MODE Port GPIO(11); See note for bits(17:16) 25:24 GPIO12_PORT_MODE Port GPIO(12); 27:26 GPIO13_PORT_MODE Port GPIO(13); 29:28 GPIO14_PORT_MODE Port GPIO(14); 31:30 GPIO15_PORT_MODE Port GPIO(15); Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 37: Timer 0 And Timer 1

    Timer 0 and Timer 1 Two independent timers are integrated in the ERTEC 400. They can be used for internal monitoring of diverse software routines. Each timer has an interrupt output that is connected to the IRQ interrupt controller of the ARM946.

  • Page 38: Mode Of Operation Of Timers

    4 bytes 0x00000000 Timer 0 value register TIM1 0x001C 4 bytes 0x00000000 Timer 1 value register Table 10: Overview of Timer Registers Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 39: Timer 0/1 Register Description

    1: Timer is loaded with the reload register value when the timer value is 00000000h and the timer continues running Reserved Not relevant (can be read/write-accessed) Reserved Not relevant (read=0) Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 40 Description Prediv (7:0) Reload value of Prescaler 0 15:8 Prediv (15:8) Reload value of Prescaler 1 31-16 Reserved Not relevant (read=0) Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 41: F - Counter

    The maximum input frequency for the F-CLK is one-quarter of the APB clock. In the event of a quartz failure on the ERTEC 400, a minimum output frequency between 40 and 90 MHz is set at the PLL. This yields a minimum APB-CLK frequency of PLLOUT 40 MHz / 6 = 6.6666 MHz.

  • Page 42: Address Assignment Of F-Timer Registers

    Description 31:16 F-CNT-RES (31:16) More significant word of F-counter reset (any value) 15:0 F-CNT-RES (15:0) Less significant word of F-counter reset Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 43: Watchdog Timers

    Watchdog Timers Two watchdog timers are integrated in the ERTEC 400. The watchdog timers are intended for stand-alone monitoring of processes. The working clock of 50 MHz is derived from the PLL the same as the processor clock. 4.5.1 Watchdog Timer 0 Watchdog timer 0 is a 32-bit down-counter to which the WDOUT0_N output is assigned.

  • Page 44: Watchdog Registers

    0: Watchdog counter 0 disabled 1: Watchdog counter 0 enabled Note: If this bit = 0, the WDOUT0_n output of the ERTEC 400 is active (0), the interrupt of the watchdog (WDINT) is “0”, and the status bit of counter 0 (Bit 3) is “0”.
  • Page 45 Description Watchdog value 1. Value of watchdog counter 1. Bit No. Name Description 31-0 WDOG1(36:4) Bit (36:4) of watchdog counter 1. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 46: Uart1/ Uart2

    UART1/ UART2 Two UARTs are implemented in the ERTEC 400. The inputs and outputs of the UARTs are available as an alternative function at GPIO port [13:9] (UART1) and GPIO port [18:14] (UART2). For this purpose, the I/O must be assigned to the relevant inputs and outputs and the alternative function must be assigned (see GPIO register description).

  • Page 47: Table 13: Baud Rates For Uart At F

    UART 1 can also be used as a BOOT medium if, for example, functions from an external PC are to be loaded to the ERTEC 400 and executed. The BOOT medium is selected by the BOOT[2:0] inputs during the active reset phase.

  • Page 48: Address Assignment Of Uart 1/2 Registers

    Parity error = 1 (Read) Parity of received character does not match the assigned parity in the UARTLCR_H register Bit 2. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 49 NOTE: The baud rate divisor is calculated according to the following formula: UARTCLK BAUDDIV = ------------------------- - 1 16 * baud rate Zero is not a valid divisor. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 50 Transmit FIFO Empty = 1 if FIFO is disabled and Transmit holding register is empty FIFO is enabled and Transmit FIFO buffer is empty Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 51 NOTE: The low power divisor is calculated according to the following formula: UARTCLK ILPDVSR = ---------------------- - 1 FIrLPBAUD16 is nominally 1.8432 MHz IrLPBAUD16 Zero is not a valid divisor. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 52: Synchronous Interface Spi

    Synchronous Interface SPI An SPI interface is implemented in the ERTEC 400. The inputs and outputs of the SPI interface are available as an alternative function at GPIO port [23:16]. For this purpose, the I/O must be assigned to the relevant inputs and outputs and the alternative function must be assigned (see GPIO register description).

  • Page 53: Address Assignment Of Spi Register

    The SPI interface can also be used as a BOOT medium if, for example, functions from a serial EEPROM are to be loaded to the ERTEC 400 and executed. The BOOT medium is selected by the BOOT[2:0] inputs during the active reset phase.

  • Page 54: Spi Register Description

    (This bit can only be changed if Bit 4 SSE = 0) 0 = Device is master (default) 1 = Device is slave Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 55 When the value is read, bit 0 is always zero. 15-5 ------------ Reserved Read: Value is undefined Write: Should always be written with zero Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 56: System Control Register

    System Control Register The system control registers are ERTEC 400-specific control registers that can be read and written to from the PCI/LBU side or from the ARM946. A listing of all system control registers and their address assignments as well as a detailed description are included in the following sections.

  • Page 57: System Control Register Description

    ID_REG Addr.: 0x4000_2600 Default: 0x4026_0100 Description Identification of ERTEC 400 Bit No. Name Description 31..16 ERTEC400-ID ERTEC 400 identifier: 4026h (corresponds to the device ID of the AHB-PCI bridge) 15..8 HW-RELEASE HW release: 01h 7..0 Reserved Reserved BOOT_REG Addr.: 0x4000_2604...
  • Page 58 1: Last reset was via a software reset WD_RESET 1: Last reset was via a watchdog PLL_STAT_REG Addr.: 0x4000_2614 Default: 0x0007_0005 Description Status register for PLL of ERTEC 400 and interrupt control for FIQ3 Bit No. Name Description 31..19 ---- Reserved...
  • Page 59 31: 2 ---- Reserved PM_STATE_REQ Required power state of the PCI host PM_STATE_ ACK_REG Addr.: 0x4000_2620 Default: 0x0000_0000 Description Current power state of the ERTEC 400 Bit No. Name Description 31:2 ---- Reserved PM_STATE_ACK Current power state of the ERTEC 400 Page Copyright ©...
  • Page 60 Address QVZ_EMIF_ADR Addr.: 0x4000_2638 Default: 0x0000_0000 Description Address that leads to timeout on EMIF Bit No. Name Description 31:0 QVZ_EMIF_ADR Address Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 61 Control of PCI interrupts Bit No. Name Description 31:2 ---- Reserved PCI_INT_CTRL[1] PCI_INT_CTRL = 0x0000_0001 IRQ0_HP SERR_N PCI_INT_CTRL = 0x0000_0000 IRQ0_HP INTB_N PCI_INT_CTRL[0] Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 62 Name Description 31:1 ---- Reserved Write enable for ARM9_CTL register WE_ARM9_CTRL 1: ARM9_CTRL can be write accessed. 0: ARM9_CTRL is read-only. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 63: General Hardware Functions

    RMII/MII – interfacing of Ethernet MACs • 5.1.1 Clock Supply in ERTEC 400 The required clocks are generated in the ERTEC 400 by means of internal PLL and/or through direct infeed. The following table provides a detailed list of the clocks: MODULE CLOCK SOURCE...

  • Page 64: Pci Clock Supply

    In MII mode, the two PHYs are supplied with one 25 MHz PHY clock. The clock for the Ethernet ports of the ERTEC 400 is supplied by the MII PHYs via the RX_CLK and TX_CLK clock cables. The clock for the Ethernet ports is enabled/disabled via the clock control register in the IRT switch.

  • Page 65: Reset Logic Of The Ertec 400

    Figure 10: Clock Supply of Ethernet Interface Reset Logic of the ERTEC 400 The reset logic resets the entire circuit of the ERTEC 400 except for the PCI portion of the AHB-PCI bridge. The reset system of the ERTEC 400 is enabled by the following events: Hardware reset via external RESET_N pin •...

  • Page 66: Watchdog Reset

    This register can be evaluated after a restart. 5.2.3 Software reset A software reset can be triggered in the ERTEC 400 by setting a bit in the reset control register. The XRES_SOFT bit is set in the reset status register when the reset is triggered. 5.2.4...

  • Page 67: Address Space And Timeout Monitoring

    If one of the four memory areas that are selected via the CS_PER0_N to CS_PER3_N chip select outputs is addressed, the memory controller of the ERTEC 400 waits for the RDY_PER_N input signal. The monitoring duration is set in the ASYNC_WAIT_CYCLE_CONFIG EMIF register and is active if timeout monitoring (Bit 7) is set in the EXTENDED_CONFIG EMIF register.
  • Page 68 To avoid irritations concerning the interrupt causes it is recommended to reset interrupt bit 4 "INT_QVZ_PCI_STATE" in register "PLL_STAT_REG" at the beginning of 2nd level boot code. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change...

  • Page 69: External Memory Interface (Emif)

    External Memory Interface (EMIF) In order to access an external memory area, an External Memory Interface is incorporated in the ERTEC 400. The interface contains one SDRAM memory controller and one SRAM memory control each for asynchronous memory. Both interfaces can be assigned separately as active interfaces. That is, the data bus is driven actively to High at the end of each access.

  • Page 70: Address Assignment Of Emif Registers

    This value multiplied by 16 is equivalent to the number of AHB clock cycles that the asynchronous controller waits for RDY_PER_N before access is terminated with timeout IRQ. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 71 1: SDRAM power-up sequence is complete 28..13 ---- Reserved 12..0 REFRESH_RATE Refresh rate Number of AHB clock cycles between 2 SDRAM refresh cycles Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 72 3..2 ---- Reserved 1..0 ASIZE Asynchronous bank size 00: 8-bit data bus 01: 16-bit data bus 1x: 32-bit data bus Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 73 After the watchdog expires (256 AHB clock cycles), an interrupt is triggered. Setting Bit 7 to 0 deletes interrupt source. 6..0 ---- Reserved Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 74: Local Bus Unit (Lbu)

    LBU_RDY_N is a tristate output and must be pulled to his “ready” level by an external pull-down or pull-up resistor. During an access from the LBU-Interface to the ERTEC 400 (CS with RD or WR activ) , the LBU_RDY_N switched to inactiv (Wait) first. LBU_RDY_N will be active for a 50 MHz-Clock if data can be read or write.

  • Page 75: Page Range Setting

    ERTEC 400. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 76: Page Control Setting

    In this case, the address area access must be assigned as "Little Endian access." Access by the host is asynchronous to the AHB clock of the ERTEC 400. For this reason, it is synchronized with the AHB clock. The following figures show different read- and write sequences with the timings: Page Copyright ©...

  • Page 77: Lbu Read From Ertec 400 With Separate Read/Write Line (Lbu_Rdy_N Active Low)

    7.3.1 LBU Read from ERTEC 400 with separate Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CS_M_N RCSH CSRS LBU_RD_N LBU_A(20:0)A/ LBU_SEG(1:0)/ LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) Figure 12: LBU-Read-Sequence with separate RD/WR line Parameter Description chip select asserted to read pulse asserted delay...

  • Page 78: Lbu Write To Ertec 400 With Separate Read/Write Line (Lbu_Rdy_N Active Low)

    7.3.2 LBU Write to ERTEC 400 with separate Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CD_M_N WCSH CSWS LBU_WR_N LBU_A(20:0)/ LBU_SEG(1:0) LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) Figure 13: LBU-Write-Sequence with separate RD/WR line Parameter Description chip select asserted to write pulse asserted delay...

  • Page 79: Lbu Read From Ertec 400 With Common Read/Write Line (Lbu_Rdy_N Active Low)

    7.3.3 LBU Read from ERTEC 400 with common Read/Write line (LBU_RDY_N active low) LBU_CS_R_N/ LBU_CS_M_N LBU_WR_N LBU_A(20:0)/ LBU_SEG(1:0)/ LBU_BE(1:0)_N LBU_RDY_N LBU_D(15:0) Figure 14: LBU-Read-Sequence with common RD/WR line Parameter Description write signal deasserted to chip select asserted setup time 2 ns...

  • Page 80: Lbu Write To Ertec 400 With Common Read/Write Line (Lbu_Rdy_N Active Low)

    LBU unit drives the ERTEC 400 databus. The ERTEC 400 has two LBU chip select inputs. One for access to the page configuration register (LBU_CS_R_N) and one to access to the ERTEC 400 memory address space (LBU_CS_M_N). Only one of these chip select signals may be active at a time and it is not allowed to chahge the chip select during the complete access.

  • Page 81: Address Assignment Of Lbu Registers

    LBU pagex offset register 3 High LBU_P3_CFG 0x0038 2 bytes 0x0000 LBU configuration register 3 Table 26: Overview of LBU Registers Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 82: Lbu Register Description

    Configuration for the individual pages Bit No. Name Description 15..1 Reserved PAGE_X_32 1: Page is a 32-bit page 0: Page is a 16-bit page Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 83: Pci Interface

    PCI Interface The AHB-PCI bridge of Fujitsu-Siemens is used as the PCI interface. A 2-Gbyte segment starting at address 0x80000000 (offset = 2 Gbytes) is on the AHB bus. See also “Detailed Memory Description“ in Section 9.2. The configuration area of the PCI macro is addressed here. Mapping of addresses of the AHB to the address area of the PCI bus can be set in the configuration area.

  • Page 84: Pci Target Interface

    "Bit 3 ARB_MODE" of the "M_LOCK_CTRL" register (address 0x4000264C) must be set by the 2nd level bootcode.Before this bit is set, you must disable all other AHB masters. See flowchart: Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 85: Pci Interrupt Handling

    (ICU) to the IRQ input of the ARM946E-S. Optionally, the option exists to link these interrupts to the ARM946E-S by assigning the ICU as FIQ. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change...

  • Page 86: Figure 16: Pci Interrupt Handling

    When used, the IRQ0_HP and IRQ_IRT_API_ERR interrupts are synchronized to the PCI clock and kept active for the duration of one PCI clock cycle. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change...

  • Page 87: Pci Power Management

    The ERTEC 400 requires the PCI clock to initiate the “PME_N” signal. If the power state of the ERTEC 400 is not D0, all PCI interrupts in the ERTEC 400 must be disabled via the software (according to the PCI specification, PCI interrupts can only be enabled in the D0 state). There is no hardware support for disabling the interrupts.

  • Page 88: Ertec 400 Applications With Pci

    ERTEC 400 in a PC System In PC systems, the ERTEC 400 can be integrated into the system as a PC card with host and master functionality. The PC card can be operated on the 32-bit bus at a maximum of 66 MHz. Interrupt INTB_N must be disabled because the PC interface of the ERTEC 400 is only a "single function interface."...

  • Page 89: Ertec 400 As A Station On The Local Pci Bus

    8.2.2 ERTEC 400 as a Station on the Local PCI Bus In contrast to PC systems, the configuration can be changed during operation in local PCI systems where a host is active on the PCI system. In systems where a PCI interface is implemented only between several ERTEC 400s, one of the ERTEC 400s can also assume the host function.

  • Page 90: Address Assignment Of Pci Register

    Reserved 0x00020000 0x008C Class_Code Revision_ID 0x00000000 0x0090 AHB_Base_Address_Register0 0x00000001 0x0094 AHB_Base_Address_Register1 0x00000000 0x0098 AHB_Base_Address_Register2 0x00000000 0x009C AHB_Base_Address_Register3 0x00000000 0x00A0 AHB_Base_Address_Register4 0x00000000 Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 91: Pci Register Description

    Table 27: Overview of PCI Registers PCI Register Description A detailed description of the individual PCI registers can be found in /3/. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 92: Memory Description

    Not used EMIF register 7FFF FFFF 8000 0000 8 - 15 Not used FFFF FFFF Table 28: Partitioning of Memory Areas Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 93: Detailed Memory Description

    Note: For size and location of areas, see "AHB-PCI Bridge" Rev.2.5, 2002, Fujitsu Siemens Computers Table 29: Detailed Description of Memory Segments Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...
  • Page 94 N. In this case, the number of mirrorings N = 8. Access to the 4 unused bytes does not result in an acknowledgement timeout, but the read or written values are undefined. Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change...

  • Page 95: 10 Test And Debugging

    10.1 ETM9 Embedded Trace Macrocell An ETM9 module is integrated in the ARM946E-S of the ERTEC 400 to enable instructions and data to be traced. The ARM946E-S supplies the ETM module with the signals needed to carry out the trace functions. The ETM9 module is operated by means of the Trace interface or JTAG interface.

  • Page 96: 10.2 Trace Interface

    10.2 Trace Interface The trace interface is parameterized, enabled, and disabled by means of a connected debugger (e.g. by Lauterbach) on the JTAG interface. A Trace port is provided in the ERTEC 400 for tracing internal processor states: PIPESTA [2:0] •...

  • Page 97: 11 Miscellaneous

    Pull Up RMII Reduced Media Independent Interface Real Time Standard Serial Peripheral Interface Software UART Universal Asynchronous Receiver / Transmitter Warteschlange (queue) Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

  • Page 98: 11.2 References

    IEEE Standard Test Access Port and Boundary-Scan Architecture (1149.1 IEEE Boundary Scan 2001.PDF); /10/ IR35-107-3.pdf /11/ LeadfreeIR50_60.pdf /12/ Codeexpl.pdf /13/ EB 400 Manual V1.2.1 (EB400_Manual_V121.PDF); /14/ ERTEC400_ERRATA_EN.PDF /15/ ERTEC_ARM_ERRATA_INFO.PDF Page Copyright © Siemens AG 2010. All rights reserved. ERTEC 400 Manual Technical data subject to change Version 1.2.2...

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