Siemens Ertec 400 Manual page 17

No Signal Name
. PCI
151 IRDY_N
152 FRAME_N
153 CBE2_N
154 AD16
155 AD17
156 AD18
157 AD19
158 AD20
159 AD21
160 AD22
161 AD23
162 IDSEL
163 CBE3_N
164 AD24
165 AD25
166 AD26
167 AD27
168 AD28
169 AD29
170 AD30
171 AD31
172 PME_N
173 REQ_N
174 GNT_N
175 CLK_PCI
176 RES_PCI_N
177 INTA_N
178 INTB_N
179 M66EN
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
Signal Name I/O
(5)
LBU (Reset)
PCI/LBU Interface
LBU_AB03 B/I (I)
LBU_AB04 B/I (I)
LBU_AB05 B/I (I)
LBU_AB06 B/I (I)
LBU_AB07 B/I (I)
LBU_AB08 B/I (I)
LBU_AB09 B/I (I)
LBU_AB10 B/I (I)
LBU_AB11 B/I (I)
LBU_AB12 B/I (I)
LBU_AB13 B/I (I)
LBU_AB14 I/I (I)
LBU_AB15 B/I (I)
LBU_AB16 B/I (I)
LBU_AB17 B/I (I)
LBU_AB18 B/I (I)
LBU_AB19 B/I (I)
LBU_AB20 B/I (I)
LBU_SEG_0 B/I (I)
LBU_SEG_1 B/I (I)
LBU_CS_R_N B/I (I)
LBU_RDY_N B/O (I)
LBU_CS_M_N O/I (T)
LBU_CFG I /I (I)
--- I /I (I)
--- I /I (I)
LBU_IRQ0_N O/O (T)
LBU_IRQ1_N O/O (T)
--- B/I (I)
Pull- Pin No.
A10
A12
A13
B12
B13
E11
A14
E12
B14
E13
B15
D13
A16
F14
B16
E14
A17
F15
B17
D14
B18
D16
A19
D17
B19
E17
D18
B20
D19
Page
17
Comment
LBU: Address Bit 3
LBU: Address Bit 4
PCI: Byte 2 Enable
LBU: Address Bit 5
PCI: Address / Data Bit 16
LBU: Address Bit 6
PCI: Address / Data Bit 17
LBU: Address Bit 7
PCI: Address / Data Bit 18
LBU: Address Bit 8
PCI: Address / Data Bit 19
LBU: Address Bit 9
PCI: Address / Data Bit 20
LBU: Address Bit 10
PCI: Address / Data Bit 21
LBU: Address Bit 11
PCI: Address / Data Bit 22
LBU: Address Bit 12
PCI: Address / Data Bit 23
LBU: Address Bit 13
PCI: IDSEL
LBU: Address Bit 14
PCI: Byte 3 Enable
LBU: Address Bit 15
PCI: Address / Data Bit 24
LBU: Address Bit 16
PCI: Address / Data Bit 25
LBU: Address Bit 17
PCI: Address / Data Bit 26
LBU: Address Bit 18
PCI: Address / Data Bit 27
LBU: Address Bit 19
PCI: Address / Data Bit 28
LBU: Address Bit 20
PCI: Address / Data Bit 29
LBU: Segment 0
PCI: Address / Data bit 30
LBU: Segment 1
PCI: Address / Data bit 31
LBU: Chip select for accesses
to paging configuration register
PCI mode: Open drain; ext. PU
necessary
LBU mode: Ready signal;
polarity dependent on
LBU_POL_RDY input; output
active while LBU_CS_R/M_N is
active;
LBU mode: Chip select for
accesses to ERTEC 400-internal
resources
LBU mode:
0 : Separate RD/WR line
1: LBU_WR_N has read/write
control
PCI bus clock
PCI bus reset
PCI mode: Open drain; ext. PU
necessary
LBU mode: No open drain
PCI mode: Open drain; ext. PU
necessary
LBU mode: No open drain
Selection of 66/33 MHz PCI
clock
ERTEC 400 Manual
Version 1.2.2