F - Counter; Figure 5: Block Diagram Of F-Counter - Siemens Ertec 400 Manual

TIM0
TIM1
Description Timer registers 0 to 1. Values of timers 0 to 1.
Bit No. Name
31:0 Timer (31:0)
4.4

F - Counter

An F-counter is integrated in the ERTEC 400 in addition to the system timers. This counter works independently
of the system clock and can be used for fail-safe applications, for example. The F-counter is triggered via the
alternative "F_CLK" function at the external "BYP_CLK" input. External triggering is not possible if the ARM946E-
S is operated in a reserved test mode (Config[4:3] = 11).
The following signal pins are available for the F-counter on the ERTEC 400.
External counter cable
•
Function description:
The asynchronous input signal of the external independent time base is applied at a synchronization stage via the
BYP_CLK input pin (alternative F_CLK function). To rule out occurrences of metastable states at the counter
input, the synchronization stage is implemented with three flip-flop stages. The count pulses are generated in a
series-connected edge detection. All flip-flops run at the APB clock of 50 MHz.
The F_COUNTER_VAL register is reset using an asynchronous block reset or by writing the value 0x XXXX 55AA
(X means "don't care) to the F-counter register "FCOUNT_RES". The next count pulse sets the counter to
0xFFFF FFFF and the counter is decremented at each additional count pulse. The FCOUNT_RES register is
cleared again at the next clock cycle.
The count value can be read out by a 32-bit read access. While an 8-bit or 16-bit read access is possible, it is not
useful because it can result in an inconsistency in the read count values.
Note on input frequency:
The maximum input frequency for the F-CLK is one-quarter of the APB clock. In the event of a quartz failure on
the ERTEC 400, a minimum output frequency between 40 and 90 MHz is set at the PLL. This yields a minimum
APB-CLK frequency of PLLOUT
the F-CLK can not exceed APB-CLKmin 6.66 MHz/4 = 1.6666 MHz
The figure below shows the function blocks of the F-counter.
CONFIG(4:3)
CLK_APB
BYP_CLK
Sync Stage:
3 stages +
DIRECT_IN
edge detect+
enable
F_CLK

Figure 5: Block Diagram of F-Counter

Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
R Addr.: 0x4000_2018
R Addr.: 0x4000_201C
Description
Value of timer
1 F_CLK
40 MHz / 6 = 6.6666 MHz. To rule out a malfunction in the edge evaluation,
min
CLK_50
32-Bit Down-Counter
F-COUNTER-EN
EN
Read: F-Counter-Val
Reset
F-Counter-Val(31:0)
APB-Bus
Page
41
Default: 0x0000_0000
Default: 0x0000_0000
Write: F-Counter-Res
FCOUNT_RES
Data = 0xXXXX 55AAh
ERTEC 400 Manual
Version 1.2.2