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to FIQPR7 are for the FIQ interrupts. A priority must not be assigned more than once. The interrupt control logic
does not check for assignment of identical priorities. All interrupt requests with a lower or equal priority can be
blocked at any time in the IRQ priority resolver by assigning a priority in the LOCKREG register. If an interrupt that
is to be blocked is requested at the same time as the write access to the LOCKREG register, an IRQ signal is
output. However, the signal is revoked after two clock cycles. If an acknowledgement is to be generated
nonetheless, the transferred interrupt vector is the default vector.
2.9.2
Trigger Modes
There are two modes available for each interrupt input: "edge-triggered" and "level-triggered".
The trigger type is defined by means of the assigned bit in the TRIGREG register. For the "Edge-triggered" mode
setting, differentiation can be made between a positive and negative edge evaluation. This is made in the
EDGEREG register. "Edge-triggered" with positive edge is the default mode assignment for all interrupts. "High" is
the active level in the "level-triggered" mode.
The interrupt input signal must be present for at least one clock cycle in "edge-triggered" mode. The input signal
must be present up until confirmation of the ARM946E-S CPU in "level-triggered" mode. Shorter signals result in
loss of the event.
2.9.3
Masking the Interrupt Inputs
Each IRQ interrupt can be enabled or disabled individually. The MASKREG register is available for this purpose.
The interrupt mask acts only after the IRREG interrupt request register. That is, an interrupt is entered in the
IRREG register in spite of the block in the MASKREG register. After a reset, all mask bits are set and, thus, all
interrupts are disabled. At a higher level, all IRQ interrupts can be disabled globally via a command. When IRQ
interrupts are enabled globally via a command, only those IRQ interrupts that are enabled by the corresponding
mask bit in the MASKREG register are enabled.
For the FIQ interrupts, only selective masking by the mask bits in the FIQ_MASKREG register is possible. After a
reset, all FIQ interrupts are disabled. A detected FIQ interrupt request is entered in the FIQ interrupt request
register. If the interrupt is enabled in the mask register, processing takes place in the priority logic. If the interrupt
request is accepted by the ARM946 CPU and an entry is made in the in-service request register (ISR), the
corresponding bit is reset in the IRREG register. Each bit that is set in the IRREG register can be deleted via
software. For this purpose, the number of the bit to be reset in the IRCLVEC register is transferred to the interrupt
controller.
2.9.4
Software Interrupts for IRQ
Each IRQ interrupt request can be triggered by setting the bit corresponding to the input channel in the SWIRREG
software interrupt register. Multiple requests can also be entered in the 16-bit SWIRREG register. The software
interrupt requests are received directly in the IRREG register and, thus, treated like a hardware IRQ. Software
interrupts can only be triggered by the ARM946E-S processor because only this processor has access rights to
the interrupt controller.
2.9.5
Nested Interrupt Structure
When enabled by the interrupt priority logic, an IRQ interrupt request causes an IRQ signal to be output. Similarly,
an FIQ interrupt request causes the FIQ signal to be output to the CPU.
If the request is accepted by the CPU (in the IRQACK or FIQACK register), the bit corresponding to the physical
input is set in the ISREG or FIQISR register. The IRQ/FIQ signal is revoked. The ISR bit of the accepted interrupt
remains set until the CPU returns an "End-of-interrupt" command to the interrupt controller. As long as the ISR bit
is set, interrupts with lower priority in the priority logic of the interrupt controller are disabled. Interrupts with a
higher priority are allowed by the priority logic to pass and generate an IRQ/FIQ signal to the CPU. As soon as the
CPU accepts this interrupt, the corresponding ISR bit in the ISREG or FIQISR register is also set. The CPU then
interrupts the lower-priority interrupt routine and executes the higher interrupt routine first. Lower-priority interrupts
are not lost. They are entered in the IRREG register and are processed at a later time when all higher-priority
interrupt routines have been executed.
2.9.6
EOI End-Of-Interrupt
A set ISR bit is deleted by the End-of-Interrupt command. The CPU must use the EOI command to communicate
this to the interrupt controller after the corresponding interrupt service routine is processed. To communicate the
EOI command to the interrupt controller, the CPU writes any value to the IRQEND/FIQEND register. The interrupt
controller autonomously decides which ISR bit is reset with the EOI command. If several ISR bits are set, the
interrupt controller deletes the ISR bit of the interrupt request with the highest priority at the time of the EOI
command. The interrupt controller regards the interrupt cycle as ended when all of the set ISR bits have been
reset by the appropriate number of EOI commands. Afterwards, low priority interrupts that occurred in the
meantime and were entered in the IRREG register can be processed in the priority logic.
During one or more accepted interrupts, the priority distribution of the IRQ/FIQ interrupt inputs must not be
changed because the ICU can otherwise no longer correctly assign the EOI commands.
An IRQ/FIQ request is accepted by the CPU by reading the IRVEC/FIVEQ register. This register contains the
binary-coded vector number of the highest priority interrupt request at the moment. Each of the two interrupt
vector registers can be referenced using two different addresses. The interrupt controller interprets the reading of
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Technical data subject to change
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ERTEC 400 Manual
Version 1.2.2
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