7.3.1
LBU Read from ERTEC 400 with separate Read/Write line (LBU_RDY_N active low)
LBU_CS_R_N/
LBU_CS_M_N
LBU_RD_N
LBU_A(20:0)A/
LBU_SEG(1:0)/
LBU_BE(1:0)_N
LBU_RDY_N
LBU_D(15:0)
Figure 12: LBU-Read-Sequence with separate RD/WR line
Parameter
t
chip select asserted to read pulse asserted delay
CSRS
t
address valid to read pulse asserted setup time
ARS
t
read pulse asserted to ready enabled delay
RRE
t
read pulse asserted to data enable delay
RDE
t
ready active pulse width
RAP
t
ready asserted to data valid delay
RTD
t
read pulse deasserted to chip select deasserted delay
RCSH
t
address valid to read pulse deasserted hold time
RAH
t
data valid/enabled to read pulse deasserted hold time
RDH
t
read recovery time
RR
Table 22: LBU read access timing with seperate Read/Write line
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
t
CSRS
t
ARS
t
RRE
t
RDE
Description
t
RAP
t
RTD
17 ns
25 ns
Page
77
t
RCSH
t
RR
t
RAH
t
RDH
Min
Max
0 ns
0 ns
5 ns
12 ns
5 ns
12 ns
23 ns
5 ns
0 ns
0 ns
0 ns
12 ns
ERTEC 400 Manual
Version 1.2.2