Reset Logic Of The Ertec 400; Hardware Reset; Figure 10: Clock Supply Of Ethernet Interface; Figure 11: Power-Up Phase Of The Pll - Siemens Ertec 400 Manual

REF_CLK
(50 MHz)

Figure 10: Clock Supply of Ethernet Interface

5.2

Reset Logic of the ERTEC 400

The reset logic resets the entire circuit of the ERTEC 400 except for the PCI portion of the AHB-PCI bridge.
The reset system of the ERTEC 400 is enabled by the following events:
Hardware reset via external RESET_N pin
•
Software reset via XRES_SOFT bit in the reset control register
•
Watchdog reset via watchdog timer overflow
•
The triggering reset event can be read out in the reset status register.
5.2.1

Hardware Reset

The external hardware reset circuitry is connected at the RESET_N pin of the ERTEC 400. If the hardware reset
is enabled, the entire ERTEC 400 circuit except for the PCI portion is reset internally. The hardware reset must be
present steadily for at least 35 µs (see figure below). Afterwards, the PLL powers up within t
lock status of the PLL is monitored. The state of the PLL can be read out in the PLL_STAT_REG status register.
In the case of the hardware reset, a bit is set in the reset status register. This bit remains unaffected by the
triggered reset function. This register can be evaluated after a restart. The following figure shows the power-up
phase of the PLL after a reset.
f/MHz

Figure 11: Power-Up Phase of the PLL

Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
ERTEC400
RMII Mode
(Interface to 4-port PHY
via RMII)
Ether- Ether- Ether-
net net net
port port port
0 1 2
Buffer Buffer Buffer
RMII RMII RMII
PHY0 PHY1 PHY2
(RMII) (RMII (RMII)
300
35
ERTEC400
(Interface to two 1-port PHYs
Ether- Ether-
net net
port port
3 0
Buffer Buffer
RMII MII
PHY3 PHY0
(RMII) (MII)
t = 400 µs
LOCK
Power-up PLL
Page
65
MII Mode
via MII)
Ether- Ether- Ether-
net net net
port port port
1 2 3
Buffer Buffer Buffer
MII RMII RMII
PHY_CLK
(25 MHz)
PHY1
(MII)
400 µs. The
Lock =
t/µs
ERTEC 400 Manual
Version 1.2.2