Agilent Technologies E8362C Service Manual page 135

REAR PANEL
E8363C and E8364C Overall Block Diagram
INTERCONNECTS
(Includes Options UNL, 014, 016, 080, 081, and H11)
Service Guide: E8364-90038
OPTION H11
W108
B
W107
R2 4
PULSE IN W106 \
R1
W105
A
W104
B
W103
8.33 MHz R2 4
A1
W102 \ RPG INVERTER
IF IN
R1 KEYPAD
W101
A
A15 CPU
USB USB
INTERFACE
M ICRO CONTROLLER
RS-232 PORT
RS-232
INTERFACE
A3 FRONT PANEL INTERFACE
PARALLEL PORT EEPROM
PARALLEL
INTERFACE
PCI BUS
MAIN
GPIB PORT CPU
GPIB
INTERFACE
ROM RAM
10/100 BASE-T
LAN
ETHERNET
VGA
VGA VIDEO PROCESSOR
INTERFACE
VIDEO RAM
A41 HARD A14 SYSTEM MOTHERBOARD
DISK DRIVE
USB
USB x 4
INTERFACE
A4
POWER
LINE IN
SUPPLY
A10 FREQUENCY REFERENCE
10 MHz
W33 200 Hz 211
EXT REF IN J2
10 MHz
B0 1.0416 MHz
100 MHz 96
212
215
ƒ 2 5
10 MHz
12
HIGH STAB
OCXO 8.333 MHz
B1-25
DAC B1 - 25
2nd LO x4
500 kHz 99.50 MHz
33.1667 MHz
10 MHz L 218
20 ƒ R 3
W34 J3 I
EXT REF OUT
217 214 J4
10 MHz
5 MHz
REF 5 MHz B0
J10 4 MHz
2 200 Hz 213
J11
PHASE LOCK REF
J12
N/C
20 MHz
5
20 MHz
REF 216 J5
W31
W32
J5
A11 PHASE LOCK
40 MHz
COUNTER
20 MHz 15 MHz
B1 - 25
700 kHz 8.333 MHz 16.667 MHz
J6
ƒ
6 MHz
312 314 316
B0
311 AQUIRE: ON
NC
DELAY COMP
313
NC RAMP CAL
317 315
318
GND
2.5 GHz OFFSET
20 MHz
LOCAL PRETUNE: 30 kHz
REF IN DIGITAL PRETUNE RAMP
DIGITAL SWEEP: 100 Hz
BUS
ANALOG RAMP
POWER
BUS
PORT 1 A16 TEST SET
BIAS
MOTHERBOARD
INPUT
DC BIAS 1
PORT 2
BIAS
INPUT
DC BIAS 2
POWER
BUS
TO
TRIGGER OUT TRIGGER OUT
A35, A17, A18, A20,
A22, A36, A37
TRIGGER IN
LOCAL
DIGITAL BUS
AUX IO
AUX O I
INTERFACE
TEST SET O I TEST SET IO
INTERFACE
HANDLER O I
HANDLER O I
INTERFACE
OPT IO N H11
W114
LO
TEST SET
W113
DRIVERS
RF
s1
m250cblk_h11
2 January 2008
A2 TOUCHSCREEN USB
DISPLAY & CONTROLLER BOARD
DISPLAY
CONTROL
USB
A6 SIGNAL PROCESSING
HUB
ADC MODULE (SPAM)
J3
300 kHz A
ADC
SPEAKER J4
R1
300 kHz
ADC
PCI BUS PCI
J5
BRIDGE
300 kHz R2
ADC
DSP
J6
300 kHz B
RAM ADC
IF Calibration
Signal
POWER BUS
LOCAL DIGITAL BUS
TO A8, A9, A11, A12, A16
HIGH DENSITY DATA BUS
POWER BUS
LOCAL DIGITAL BUS
MIXED POWER AND CONTROL SIGNALS
SERIAL TEST BUS NODES
Bx = ACTIVE SOURCE BAND
A8 FRACTIONAL-N SYNTHESIZER A17 L.O. MULTIPLIER/AMPLIFIER
B3-25
BIAS/RF
ALC 1 1
1.5 - 3.0 GHz
LOCAL VCO 416
3 GHz
DIGITAL 413 412 1.5 GHz
W19
BUS B2 B2-25
2
B0-3
POWER J106 B2-25
B0-1
BUS
1 GHz
FRAC-N
B0-1 W20 B0-1 B4-25
LOGIC
J101
5 MHz REF J105
2250 MHz
VCO 2.4 GHz 750 MHz
415 417
L
R I
1V/GHz
(TO A12, ALC
FRAC-N
A16)
LOGIC
414 418
Level
Adjust
411
+5V REF
OPTION 080
A9 FRACTIONAL-N SYNTHESIZER A13 FREQUENCY OFFSET RECEIVER
B3-25
ALC
1.5 - 3.0 GHz
LOCAL VCO 916
3 GHz 1.5 GHz
DIGITAL 913 912 J3
B2 B2-25 W91 J4
BUS LO OUT
2
POWER J106
B0-1
BUS
1 GHz
FRAC-N W92 J2
B0-1
LOGIC
5 MHz
W115 REF J101
J105
2250 MHz
RECEIVER
915 VCO 917 2.4 GHz 750 MHz
L
R I
RF IN
FRAC-N ALC
LOGIC
914 918
Level
Adjust
911
+5V REF
W93
A12 SOURCE 20
LOCAL
DIGITAL BUS
SOURCE 10
POWER
BUS
5.25 GHz 11 GHz
MULTIPLIER/AMPLIFIER 20 (MA 20)
FM 8.0 GHz
YTO
B4-25
3-10 GHz
B4-25
YTO TUNE
B0-3
117 B0-3
3 GHz
R ALC
I
L
113 112
3.8 GHz
SLOPE
COMPENSATION
PMYO 114
1V/GHz 111
3.8 GHz
118 (FROM A11)
DAC 115
TEMP COMP
116
POWER DAC
DAC
A35 RECEIVER MOTHERBOARD
W25
W26
To
Phase Lock A
2nd LO a
A31 RECEIVER A
W27 8.333 MHz
B0-15
L
0° I R
+ 15 dB
B1-25
+ 15 dB
W28
41.667 B0
90° I R
kHz L B16-25
1.0416 MHz
2nd LO b
To
Phase Lock R1
2nd LO a
A32 RECEIVER R1
8.333 MHz
L B0-15
0° I
R
+ 15 dB
B1-25
+ 15 dB
B0
41.667 90° I R
L B16-25
kHz
1.0416 MHz
2nd LO b
Phase Lock R2 To
2nd LO a
A33 RECEIVER R2
8.333 MHz
L B0-15
0° I R
+ 15 dB + 15 dB
B1-25
+ 15 dB + 15 dB
B0
41.667 90° I R
kHz L B16-25
To 2nd LO a x 4
1.0416 MHz
B0 1.000 MHz 0°
B1 - 25 8.29167 MHz 0°
2nd LO b
W29
J2
4
To 2nd LO b x 4 To
Phase Lock B
2nd LO a
B0 1.000 MHz 9 0°
B1 - 25 8.29167 MHz 9 0° A34 RECEIVER B
8.333 MHz
B0-15
L
0° I
R
A + 15 dB
B1-25
W30 J50 R1
PHASE PHASE + 15 dB
LOCK LOCK B0
MUX 41.667 90° I R
MUX R2
kHz L B16-25
1.0416 MHz
B
2nd LO b
J502
W116
FROM A13J6
10 (LOMA 10) A18 MULTIPLIER/AMPLIFIER
MULTIPLIER/AMPLIFIER 20 (MA 20)
LOMA10
2 2
11 GHz
W18
3.0 - 3.8 GHz
3.8 - 4.8 GHz
B4 - 7, 11, 19 - 20
X2 X2
6.0 - 7.6 GHz
B8 -10, 12 - 18, 21 - 25
4.8 - 6.0 GHz
X2
7.6 - 10.0 GHz
516
-15V REF
517
+9V REF
518
+15V REF
FROM FROM FROM
A16 A16 A16
A16 TEST SET MOTHERBOARD
LO IN
OPTION H11
PL OUT J6 W116
L TO A35 A47
R I
J502 RF CO UP ER L
W109 W111
W113
4 4
0.01-20 GHz
R1
R2
11 GHz
B0-10 23 GHz
B11-25
15 GHz 10.0-12.8 GHz
12.8 - 16.0 GHz
X2
16.0 - 20.0 GHz
O TION H1 P 1
4 4
MIXER BIAS
A49 IF MULTIPLEXER A27 A FIRST LO
CONVERTER
3 MHz (MIXER)
B0
40 MHz
W41 J103 J101 W21 IF
L L
I I R R
B0 = 1.0416 MHz
B1-25 B1 - 25 = 8.333 MHz
50
W101
J102
W105
J104
50
A PULSE IN
A28 R1 FIRST LO
CONVERTER
3 MHz (MIXER)
B0
40 MHz
W42 J203 J201
W22 IF L L
I I
R R
B0 = 1.0416 MHz
B1-25 B1 - 25 = 8.333 MHz
50
W102
J202
W106
J204
50
R1 PULSE IN
A29 R2 FIRST LO
CONVERTER
3 MHz (MIXER)
B0
40 MHz
J303
W43 J301 W23 IF L
I R
B0 = 1.0416 MHz
B1-25
B1 - 25 = 8.333 MHz
50
J302 W103
J304 W107
50
R2 PULSE IN
LO
A30 B FIRST
CONVERTER
3 MHz (MIXER)
B0
40 MHz
W44 J403 J401 W24 IF
L
I
R
B0 = 1.0416 MHz
B1-25 B1 - 25 = 8.333 MHz
50
W104
J402
W108
J404
50
B PULSE IN
+5V
P1 J1
FROM FROM
W36
A16 A16
FROM
FROM A16J15
A16
OPT IO N H11
A19
SPLITTER
A48 A48
LO LO CO CO UP ER UP ER L L
11 GHz
B0-10, 16 - 18 23 GHz 0.01-20
W110 W112
GHz
B11 - 15, 19 - 25
15.0 GHz 10.0-12.8 GHz
12.8 - 16.0 GHz W114
X2
16.0 - 20.0 GHz
511
FROM
FROM A16
A16
A22 SWITCH
SPLITTER
A21 SOURCE MULTIPLIER/ E8364B ONLY
AMPLIFIER 50 (SOMA 50) 40-50 GHz
5 5
X2
50
20.0-25.6 GHz
B23-25 W2
50
45 GHz
25.6-32.0 GHz
B16-25
X2
B0-15 32.0-40.0 GHz
B16-22
SOMA 50 SOURCE ALC
817
DRIVE
711 W39
BREAKPOINT 1
712
BREAKPOINT 2
714
617 OFFSET
R1 R1 R1 611
LOG AMP
612
FROM
R2 R2 R2 614
716 1V/GHz A16
(FROM A11)
615 717 613
TEMP COMP
616
SLOPE COMP
718
618
PRELEVEL DAC
POWER DAC
715
+10V REF
MA 20 LO ALC
811
-10V REF
512
812
POWER DAC +1.78V BIAS REF
513 814
TO
+10V REF
A18
713 514
1V/GHz 815
-1.25V BIAS REF
(FROM A11)
816
+5V REF
515 813
SLOPE COMP PHASE LOCK IF DET
818
DET VOLTAGE OUT
OPT
W69
W67
OPTION 016
A43 STEP
ATTEN
W47 W49
TO RCVR
A27 A IN
0-35 dB
FROM
A16
RF RF W69
W70
W65
OPTION 081
A45 SWITCH
FROM
50 A16
W99
TO W98
W70 A28 50 RCVR
RF RF
R1 IN
W97
SOURCE
W96
OUT
A46 SWITCH
50
W95
50
FROM
A16
FROM
A23
W71 W71
RF
W66
W40 W14
W72 W72
RF
W68
OPTION 016
A44 STEP
ATTEN
W48 W50
TO RCVR
A30 B IN
0-35 dB
FROM
A16
3 3
A20 L.O. DISTRIBUTION
ASSY (LODA)
W11
A
W15
W12
R1
W16
W13
R2
W14
B
FROM
A16
A23 DETECTOR
W3 W65
W37
A24 DETECTOR
W4
W66
OPTION 014
W38
W61
W63
A25
W61 W63
TEST PORT
COUPLER
OPTION UNL
To W60
DC BIAS 1
A36 STEP A38
W67
ATTEN BIAS TEE
W81 W83
W51 W55
OPT ON 014
0-60 dB
FROM
A16
W62
W64
A26
W62 W64
TEST PORT
COUPLER
OPTION UNL
To W60 DC BIAS 2
A37 STEP A39
ATTEN BIAS TEE W68
W82 W82 W84 W84
W52 W56
FROM FROM FROM 0-60 dB
A16 A16 A16
FRONT PANEL
INTERCONNECTS
USB x 2
IO N 01 4
Port 1
RCVR
A IN
W60
CPLR ARM
Reference 1
RCVR
R1 IN
W60
SOURCE OUT
Reference 2
RCVR
R2 IN
W60
SOURCE OUT
Port 2
RCVR
B IN
W60
CPLR ARM
Port 1
SOURCE
OUT
W60
CPLR
THRU
PORT 1
I
Port 2
SOURCE
OUT
W60
CPLR
THRU
PORT 2