Agilent Technologies E8362C Service Manual page 131

REAR PANEL
E8362C Overall Block Diagram
INTERCONNECTS
(Includes Option UNL, 014, 016, 080, 081, and H11)
Service Guide: E8364-90038
OPT IO N H11
W108
B
W107
R2 4
PULSE IN W106 \
R1
W105
A
W104
B
W103
8.33 MHz R2 4
W102 A1
IF IN \ RPG INVERTER
R1
KEYPAD
W101
A
A15 CPU
USB
USB
INTERFACE
M ICRO CONTROLLER
RS-232 RS-232 PORT
INTERFACE
A3 FRONT PANEL INTERFACE
PARALLEL PORT EEPROM
PARALLEL
INTERFACE
PCI BUS
MAIN
CPU
GPIB GPIB PORT
INTERFACE
ROM RAM
10/100 BASE-T
LAN
ETHERNET
VGA VIDEO PROCESSOR
VGA
INTERFACE
VIDEO RAM
A41 HARD A14 SYSTEM MOTHERBOARD
DISK DRIVE
USB
USB x 4
INTERFACE
A4
POWER
LINE IN
SUPPLY
A10 FREQUENCY REFERENCE
10 MHz
200 Hz
W33 J2 211
EXT REF IN
10 MHz
B0 1.0416 MHz
96
100 MHz
212
215
2 5
ƒ
10 MHz
HIGH STAB 12
8.333 MHz
OCXO
B1-15
DAC B1 - 15
2nd LO x4
500 kHz 99.50 MHz
33.1667 MHz
L
10 MHz 218
W34 20 ƒ I R 3
EXT REF OUT J3
10 MHz J4
217 214
5 MHz
REF 5 MHz B0
J10 4 MHz
200 Hz 213
2
J11
PHASE LOCK REF
J12
N/C
20 MHz
5
20 MHz
REF 216
J5
W31
W32
A11 PHASE LOCK J5
40 MHz
COUNTER
20 MHz 15 MHz
B1 - 15
700 kHz 8.333 MHz 16.667 MHz
J6
ƒ
6 MHz
312
314 316
B0
311
AQUIRE: ON
NC
DELAY COMP
313
NC RAMP CAL
317 315
318
GND
2.5 GHz OFFSET
20 MHz
LOCAL PRETUNE: 30 kHz
REF IN DIGITAL PRETUNE RAMP
DIGITAL SWEEP: 100 Hz
BUS
ANALOG RAMP
POWER
BUS
PORT 1
A16 TEST SET
BIAS
MOTHERBOARD
INPUT
DC BIAS 1
PORT 2
BIAS
INPUT TO
A35, A17, A18, A20,
A22, A36, A37
DC BIAS 2
POWER
BUS
TRIGGER OUT TRIGGER OUT
TRIGGER IN
LOCAL
DIGITAL BUS
AUX IO
AUX O I
INTERFACE
TEST SET IO
TEST SET O I
INTERFACE
HANDLER O I
HANDLER O I
INTERFACE
O TION H11 P
W114
LO
TEST SET
DRIVERS W113
RF
s1
m220cblk_h11
2 January 2008
A2 TOUCHSCREEN USB
DISPLAY & CONTROLLER BOARD
DISPLAY
CONTROL
USB
A6 SIGNAL PROCESSING
HUB
ADC MODULE (SPAM) J3
300 kHz A
ADC
SPEAKER J4
300 kHz R1
ADC
PCI BUS
PCI
J5
BRIDGE
300 kHz R2
ADC
DSP
J6
B
300 kHz
ADC
RAM
IF Calibration
Signal
POWER BUS
LOCAL DIGITAL BUS
TO A8, A9, A11, A12, A16
HIGH DENSITY DATA BUS
POWER BUS
LOCAL DIGITAL BUS
MIXED POWER AND CONTROL SIGNALS
SERIAL TEST BUS NODES
Bx = ACTIVE SOURCE BAND
A8 FRACTIONAL-N SYNTHESIZER A17 L.O. MULTIPLIER/AMPLIFIER
B3-15
BIAS/RF
ALC 1 1
1.5 - 3.0 GHz
416
LOCAL VCO
DIGITAL 413 412 3 GHz 1.5 GHz
BUS B2 B2-15 W19
2
POWER B2-15 B0-3
J106
BUS B0-1
1 GHz
FRAC-N
W20
LOGIC B0-1 B0-1 B4-15
5 MHz REF J105 J101
2250 MHz
VCO
415 417 2.4 GHz 750 MHz
L
R I
1V/GHz
(TO A12,
FRAC-N ALC
A16)
LOGIC
414 418
Level
411 Adjust
+5V REF
OPTION 080
A9 FRACTIONAL-N SYNTHESIZER A13 FREQUENCY OFFSET RECEIVER
B3-25
ALC
1.5 - 3.0 GHz
916
LOCAL VCO
DIGITAL 913 912 3 GHz 1.5 GHz
J4 J3
BUS B2 B2-25 W91
2 LO OUT
POWER
J106
BUS B0-1
1 GHz
FRAC-N
B0-1 W92 J2
LOGIC
5 MHz
J101
W115 REF J105
2250 MHz
RECEIVER
VCO
915 917 2.4 GHz 750 MHz
L
R I
RF IN
FRAC-N ALC
LOGIC
914 918
Level
911 Adjust
+5V REF
W93
A12 SOURCE 20
LOCAL
DIGITAL BUS
SOURCE 10
POWER
BUS 5.25 GHz 11 GHz
MULTIPLIER/AMPLIFIER 20 (MA 20)
FM 8.0 GHz
YTO
B4-15
3-10 GHz
B4-15
YTO TUNE
B0-3
117 B0-3
3 GHz
R
ALC
I
L
113 112
3.8 GHz
SLOPE
COMPENSATION
PMYO
114 111
3.8 GHz 1V/GHz
118 (FROM A11)
115
DAC TEMP COMP
116
POWER DAC
DAC
A35 RECEIVER MOTHERBOARD
W25
W26
To
A
2nd LO a Phase Lock
A31 RECEIVER A
W27
8.333 MHz
L
0°
I R
+ 15 dB
B1-15
W28 B0
41.667 90° I R
kHz L
1.0416 MHz
2nd LO b
To
Phase Lock R1
2nd LO a
A32 RECEIVER R1
8.333 MHz
L
0° I R
+ 15 dB
B1-15
B0
90°
41.667 I R
L
kHz
1.0416 MHz
2nd LO b
To
Phase Lock R2
2nd LO a
A33 RECEIVER R2
8.333 MHz
L
0° I R
+ 15 dB + 15 dB
B1-15
B0
41.667 90° I R
kHz L
To 2nd LO a x 4
1.0416 MHz
B0 1.000 MHz 0°
B1 - 15 8.29167 MHz 0° 2nd LO b
W29
J2
4
To 2nd LO x 4 To
b B
2nd LO a Phase Lock
B0 1.000 MHz 9 0°
A34 RECEIVER B
B1 - 15 8.29167 MHz 9 0°
8.333 MHz
L
0° I R
A + 15 dB
B1-15
W30 J50 PHASE PHASE R1
LOCK LOCK B0
41.667 90°
MUX R2 I R
MUX L
kHz
B 1.0416 MHz
2nd LO b
J502
W116
FROM A13
J6
10 (LOMA 10) A18 MULTIPLIER/AMPLIFIER
MULTIPLIER/AMPLIFIER 20 (MA 20)
LOMA10
2 2
11 GHz
W18
3.0 - 3.8 GHz
3.8 - 4.8 GHz B4 - 7, 11
X2 X2
6.0 - 7.6 GHz
B8 -10, 12 - 15
4.8 - 6.0 GHz
X2
7.6 - 10.0 GHz
516
-15V REF
517
+9V REF
518
+15V REF
FROM
A16
OPT IO N H11
LO IN
A47
RF COUPLER
W109 W1 W111
PL OUT J6 W116
L
TO A35
R I
J502
W113
4 4
0.01-20 GHz
11 GHz
B0-10 23 GHz
B11-15
15 GHz 10.0-12.8 GHz
12.8 - 16.0 GHz
X2 A16 TEST SET MOTHERBOARD
16.0 - 20.0 GHz
MA 20 LO ALC
POWER DAC
1V/GHz
(FROM A11)
SLOPE COMP
OPT ON H11 I
4 4
A49 IF MULTIPLEXER MIXER BIAS
A27 A FIRST LO
CONVERTER
3 MHz (MIXER)
B0
40 MHz
J103
W41 J101 W21 IF L L
I I R R
B0 = 1.0416 MHz
B1-15 B1 - 15 = 8.333 MHz
50
J102 W101
J104 W105
50
A PULSE IN
LO
A28 R1 FIRST
CONVERTER
3 MHz (MIXER)
B0
40 MHz
J203
W42 J201 W22 IF L L
I I R R
B0 = 1.0416 MHz
B1-15
B1 - 15 = 8.333 MHz
50
J202 W102
J204 W106
50
R1 PULSE IN
A29 R2 FIRST LO
CONVERTER
3 MHz (MIXER)
B0
40 MHz
W43 J303 W23 IF
J301 L
I R
B0 = 1.0416 MHz
B1-15 B1 - 15 = 8.333 MHz
50
W103
J302
W107
J304
50
R2 PULSE IN
A30 B FIRST LO
CONVERTER
(MIXER)
3 MHz
B0
40 MHz
J403
W44 J401 W24 IF L
I R
B0 = 1.0416 MHz
B1-15 B1 - 15 = 8.333 MHz
50
J402 W104
J404 W108
50
B PULSE IN
+5V
P1 J1
FROM FROM
W36
A16 A16
FROM
A16 FROM A16J15
O TION H11 P
A19
SPLITTER
A48 A48
L L O O COUPLER COUPLER
11 GHz
B0-10, 16 - 18 23 GHz 0.01-20
W110
GHz W112
B11 - 15
15.0 GHz 10.0-12.8 GHz
12.8 - 16.0 GHz
W114
X2
16.0 - 20.0 GHz
511
FROM
FROM
A16
A16
A22 SWITCH
SPLITTER
50
50
FROM
A16
715
+10V REF
811
-10V REF
512
812
+1.78V BIAS REF
513
TO 814
+10V REF
A18
713 514
815
-1.25V BIAS REF
816
+5V REF
515 813
PHASE LOCK IF DET
818
DET VOLTAGE OUT
OPT
W69
W67
OPTION 016
A43 STEP
ATTEN
W47 W49
TO RCVR
A27 A IN
0-35 dB
FROM
A16
RF RF W69
W70
W65
OPTION 081
A45 SWITCH
FROM
50 A16
W99
TO
W98
A28 RCVR
RF RF W70 50
R1 IN
W97
W96 SOURCE
OUT
A46 SWITCH
50
W95
50
FROM
A16
FROM
A23
W71 W71
RF
W66
W40 W14
RF W72 W72
W68
OPTION 016
A44 STEP
ATTEN
W48 W50
TO RCVR
A30 B IN
0-35 dB
FROM
A16
3 3
A20 L.O. DISTRIBUTION
ASSY (LODA)
W11
A
W15 W12
R1
W16
W13
R2
W14
B
FROM
A16
30 db ATTENUATOR
W3
W65
30 db ATTENUATOR
W4 W66
OPT ON 014
A25
W61 W63
TEST PORT
COUPLER
OPTION UNL
To W60 DC BIAS 1
A36 STEP A38 W67
ATTEN BIAS TEE
W81 W83
W51 W55
OPT
FROM 0-60 dB
A16
A26
W62 W64
TEST PORT
COUPLER
OPTION UNL
To W60 DC BIAS 2
A37 STEP A39
ATTEN W82 W82 W84 W84 BIAS TEE W68
W52 W56
0-60 dB
FROM FROM FROM
A16 A16 A16
FRONT PANEL
INTERCONNECTS
USB x 2
ION 01 4
Port 1
RCVR
A IN
W60
CPLR ARM
Reference 1
RCVR
R1 IN
W60
SOURCE OUT
Reference 2
RCVR
R2 IN
W60
SOURCE OUT
Port 2
RCVR
B IN
W60
CPLR ARM
I
Port 1
SOURCE
OUT
W60
CPLR
THRU
PORT 1
IO N 01 4
Port 2
SOURCE
OUT
W60
CPLR
THRU
PORT 2