Appendix C: Master Constraints File Listing; Introduction; Vcu1287 Board Xdc Listing - Xilinx VCU1287 User Manual

Master Constraints File Listing

Introduction

The VCU1287 board master Xilinx design constraints (XDC) file template provides for
designs targeting the VCU1287 UltraScale FPGA GTH and GTY Transceiver Characterization
Board. Net names in the listed constraints correlate with net names on the VCU1287 board
schematic. Identify the appropriate pins and replace the net names with net names in the
user RTL. See the Vivado Design Suite User Guide: Using Constraints (UG903)
information.
See the
IMPORTANT:
latest XDC file.

VCU1287 Board XDC Listing

#FMC1
set_property PACKAGE_PIN AB32
set_property IOSTANDARD
set_property PACKAGE_PIN AF32
set_property IOSTANDARD
set_property PACKAGE_PIN AF33
set_property IOSTANDARD
set_property PACKAGE_PIN AG31
set_property IOSTANDARD
set_property PACKAGE_PIN AG32
set_property IOSTANDARD
set_property PACKAGE_PIN N32
set_property IOSTANDARD
set_property PACKAGE_PIN N33
set_property IOSTANDARD
set_property PACKAGE_PIN P31
set_property IOSTANDARD
set_property PACKAGE_PIN N31
set_property IOSTANDARD
#FMC1 LA
set_property PACKAGE_PIN AD33
set_property IOSTANDARD
set_property PACKAGE_PIN AE33
VCU1287 Characterization Board
UG1121 (v1.0) December 11, 2015
Xilinx Virtex UltraScale FPGA VCU1287 Characterization Kit website
[get_ports "FMC1_PRSNT_M2C_L"]
LVCMOS18 [get_ports "FMC1_PRSNT_M2C_L"]
[get_ports "FMC1_CLK0_M2C_P"]
LVCMOS18 [get_ports "FMC1_CLK0_M2C_P"]
[get_ports "FMC1_CLK0_M2C_N"]
LVCMOS18 [get_ports "FMC1_CLK0_M2C_N"]
[get_ports "FMC1_CLK1_M2C_P"]
LVCMOS18 [get_ports "FMC1_CLK1_M2C_P"]
[get_ports "FMC1_CLK1_M2C_N"]
LVCMOS18 [get_ports "FMC1_CLK1_M2C_N"]
[get_ports "FMC1_CLK2_BIDIR_P"]
LVCMOS18 [get_ports "FMC1_CLK2_BIDIR_P"]
[get_ports "FMC1_CLK2_BIDIR_N"]
LVCMOS18 [get_ports "FMC1_CLK2_BIDIR_N"]
[get_ports "FMC1_CLK3_BIDIR_P"]
LVCMOS18 [get_ports "FMC1_CLK3_BIDIR_P"]
[get_ports "FMC1_CLK3_BIDIR_N"]
LVCMOS18 [get_ports "FMC1_CLK3_BIDIR_N"]
[get_ports "FMC1_LA00_CC_P"]
LVCMOS18 [get_ports "FMC1_LA00_CC_P"]
[get_ports "FMC1_LA00_CC_N"]
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Appendix C
[Ref 3] for more
for the
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