Dctl - Device Control; Dctl - Device Control Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

6.2.36

DCTL - Device Control

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Table 59. DCTL - Device Control Register (Sheet 1 of 2)
Default
Bit Access
Value
15 RO
14:12 RO 000b
11 RO
10 RO
9 RO
8 RO
7:5 RW 000b
4 RO
3 RW
2 RW
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
114
RST/
PWR
0h Core Reserved
Core Reserved for Max Read Request Size (MRRS)
0b Core Reserved for Enable No Snoop (RSVD)
0b Core Reserved
Reserved for Auxiliary (AUX) PM Enable ()
0b Core Reserved
Reserved for Phantom Functions Enable ()
0b Core Reserved
Reserved for Extended Tag Field Enable ()
Core Max Payload Size (MPS)
000:128B max supported payload for Transaction Layer Packets
(TLP). As a receiver, the Device must handle TLPs as large as the
set value; as transmitter, the Device must not generate TLPs
exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to
support compliance testing.
0b Core Reserved for Enable Relaxed Ordering (RSVD)
0b Core Unsupported Request Reporting Enable (URRE)
When set, allows signaling ERR_NONFATAL, ERR_FATAL, or
ERR_CORR to the Root Control register when detecting an
unmasked Unsupported Request (UR). An ERR_CORR is signaled
when an unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL or ERR_NONFATAL is sent to the Root Control register
when an uncorrectable non-Advisory UR is received with the
severity bit set in the Uncorrectable Error Severity register.
0b Core Fatal Error Reporting Enable (FERE)
When set, enables signaling of ERR_FATAL to the Root Control
register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.
Processor Configuration Registers
0/6/0/PCI
A8-A9h
0000h
RO; RW
16 bits
Description
® ®
Celeron Processor P4505, U3405 Series
August 2010
Document Number: 323178-003