Lsts2 - Link Status 2; Lsts2 - Link Status 2 Register - Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet

Table 69. LCTL2 - Link Control 2 Register (Sheet 3 of 3)
Bit Access
6 RW-S
5 RW
4 RW-S
3:0 RW
6.2.47

LSTS2 - Link Status 2

B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Table 70. LSTS2 - Link Status 2 Register (Sheet 1 of 2)
Bit Access
15:1 RO
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
132
Default RST/
Value PWR
0b Core Selectable De-emphasis (selectabledeemphasis):
Encodings:
1b) -3.5dB
0b -6 dB
Default value is implementation specific, unless a specific
value is required for a selected form factor or platform. When
the Link is operating at 2.5GT/s speed, the setting of this bit
has no effect. Components that support only the 2.5GT/s
speed are permitted to hardwire this bit to 0b.
0b Core Hardware Autonomous Speed Disable (HASD):
When set to 1b this bit disables hardware from changing the
link speed for reasons other than attempting to correct
unreliable link operation by reducing link speed.
0b Core Enter Compliance (EC):
Software is permitted to force a link to enter Compliance
mode at the speed indicated in the Target Link Speed field by
setting this bit to 1b in both components on a link and then
initiating a hot reset on the link.
1h Core Target Link Speed (TLS):
operational speed by restricting the values advertised by the
upstream component in its training sequences. Defined
encodings are:
0001b 2.5Gb/s Target Link Speed
All other encodings are reserved.
If a value is written to this field that does not correspond to a
speed included in the Supported Link Speeds field, the result
is undefined. The default value of this field is the highest link
speed supported by the component (as reported in the
Supported Link Speeds field of the Link Capabilities Register)
unless the corresponding platform / form factor requires a
different default value. For both Upstream and Downstream
ports, this field is used to set the target compliance mode
speed when software is using the Enter Compliance bit to
force a link into compliance mode.
Default RST/
Value PWR
0000h Core
Description
For Downstream ports, this field sets an upper limit on link
0/6/0/PCI
D2-D3h
0000h
RO;
16 bits
Description
Reserved (Rsvd):
® ®
Celeron Processor P4505, U3405 Series
Processor Configuration Registers
August 2010
Document Number: 323178-003