Intel CELERON PROCESSOR P4505 - DATASHEET ADDENDUM Datasheet page 131

Processor Configuration Registers
Table 69. LCTL2 - Link Control 2 Register (Sheet 2 of 3)
Bit Access
12 RW-S
11 RW-S
10 RW-S
9:7 RW-S
® TM
Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
August 2010
Document Number: 323178-003
Default RST/
Value PWR
0b Core Compliance De-emphasis (ComplianceDeemphasis):
This bit sets the de-emphasis level in Polling.Compliance
state if the entry occurred due to the Enter Compliance bit
being 1b.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit
has no effect. Components that support only 2.5 GT/s speed
are permitted to hardwire this bit to 0b. For a Multi-Function
device associated with an Upstream Port, the bit in Function
0 is of type RWS, and only Function 0 controls the
component's Link behavior. In all other Functions of that
device, this bit is of type RsvdP. The default value of this bit
is 0b. This bit is intended for debug, compliance testing
purposes. System firmware and software is allowed to
modify this bit only during debug or compliance testing.
0b Core Compliance SOS (compsos):
Sets periodically in between the (modified) compliance
patterns. For a Multi-Function device associated with an
Upstream Port, the bit in Function 0 is of type RWS, and only
Function 0 controls the component's Link behavior. In all
other Functions of that device, this bit is of type RsvdP. The
default value of this bit is 0b. Components that support only
the 2.5 GT/s speed are permitted to hardwire this field to 0b.
0b Core Enter Modified Compliance (entermodcompliance):
When this bit is set to 1b, the device transmits modified
compliance pattern if the LTSSM enters Polling.Compliance
state. Components that support only the 2.5GT/s speed are
permitted to hardwire this bit to 0b. Default value of this field
is 0b.
000b Core Transmit Margin (txmargin):
This field controls the value of the non-de-emphasized
voltage level at the Transmitter pins. This field is reset to
000b on entry to the LTSSM Polling.Configuration substate
(see Chapter 4 for details of how the transmitter voltage
level is determined in various states).
Encodings:
000: Normal operating range
001: 800-1200 mV for full swing and 400-700 mV for half-
swing
010 - (n-1): Values must be monotonic with a non-zero
slope. The value of n must be greater than 3 and less than 7.
At least two of these must be below the normal
operating range 200-400 mV for full-swing and 100-200 mV
for half-swing -
111: reserved
Default value is 000b.
Components that support only the 2.5GT/s speed are
permitted to hardwire this bit to 0b.
Description
When set to 1b, the LTSSM is required to send SKP Ordered
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Celeron Processor P4505, U3405 Series
Datasheet Addendum
131